MAX1156 Datasheet, PDF (8/15 Pages) Maxim Integrated Products – 14-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range

14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
t_CSL
t_CSH
CS
t_ACQ
R/C
REF POWER-
DOWN CONTROL
t_DH
t_DS
t_DV
t_EOC
EOC
t_CONV
t_DO
HBEN
D7/D15–D0/D8
HIGH-Z
Figure 2. MAX1156/MAX1158/MAX1174 Timing Diagram
t_DO
t_DO1
HIGH/LOW
BYTE VALID
t_BR
HIGH/LOW
BYTE VALID
HIGH-Z
Power-Down Modes
Select standby mode or shutdown mode with the R/C
bit during the second falling edge of CS (see the
Selecting Standby or Shutdown Mode section). The
MAX1156/MAX1158/MAX1174 automatically enter
either standby mode (reference and buffer on) or shut-
down (reference and buffer off) after each conversion,
depending on the status of R/C during the second
falling edge of CS.
Internal Clock
The MAX1156/MAX1158/MAX1174 generate an internal
conversion clock to free the microprocessor from the
burden of running the SAR conversion clock. Total con-
version time (t_CONV) after entering hold mode (second
falling edge of CS) to end of conversion (EOC) falling is
4.7µs (max).
Applications Information
Starting a Conversion
CS and R/C control acquisition and conversion in the
MAX1156/MAX1158/MAX1174 (see Figure 2). The first
falling edge of CS powers up the device and puts it in
acquire mode if R/C is low. The convert start is ignored
if R/C is high. The MAX1156/MAX1158/MAX1174 need
at least 12ms (C_REFADJ = 0.1µF, C_REF = 10µF) for the
internal reference to wake up and settle before starting
the conversion, if powering up from shutdown.
+5V ANALOG +5V DIGITAL
0.1µF
0.1µF
AV_DD
ANALOG INPUT AIN
DV_DD
D0–D7
OR
D8–D13
µP DATA
BUS
MAX1156
MAX1158
EOC
R/C
MAX1174
REF
CS
REFADJ
HBEN
HIGH
AGND DGND
BYTE
0.1µF
10µF
LOW
BYTE
Figure 3. Typical Application Circuit for the MAX1156/MAX1158/
MAX1174
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