MAX1123 Datasheet, PDF (8/17 Pages) Maxim Integrated Products – 1.8V, 10-Bit, 210Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications

1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
Typical Operating Characteristics (continued)
(AV_CC = OV_CC = 1.8V, AGND = OGND = 0, f_SAMPLE = 210.0057MHz, -0.5dBFS; see TOCs for detailed information on test condi-
tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential R_L = 100Ω, T_A = +25°C.)
SINAD vs. CLOCK DUTY CYCLE (f_IN = 1.4106MHz,
f_SAMPLE = 210.0428MHz, A_IN = -0.5dBFS)
60
59
58
57
56
55
54
53
52
51
50
30 36 42 48 54 60 66 72
CLOCK DUTY CYCLE (%)
NOISE POWER RATIO PLOT
-40
-50
-60
-70
-80
-90
f_SAMPLE = 210MHz
-100 ^{fNOTCH = 28.8MHz}
NPR = 53.6dB
5 10 15 20 25 30 35
ANALOG INPUT FREQUENCY (MHz)
Pin Description
PIN
1, 6, 11–14, 20, 25,
62, 63, 65
2, 5, 7, 10, 15, 16,
18, 19, 21, 24, 64,
66, 67, EP
NAME
AV_CC
FUNCTION
Analog Supply Voltage. Bypass each pin with a 0.1µF capacitor for best decoupling results.
AGND Analog Converter Ground. Connect the converter’s exposed paddle (EP) to AGND.
Reference Input/Output. With REFADJ pulled high through a 1kΩ resistor, this I/O port allows
3
REFIO an external reference source to be connected to the MAX1123. With REFADJ pulled low
through the same 1kΩ resistor, the internal 1.23V bandgap reference is active.
Reference-Adjust Input. REFADJ allows for full-scale range adjustments by placing a resistor
or trim potentiometer between REFADJ and AGND (decreases FS range) or REFADJ and
4
REFADJ ^{REFIO (increases FS range). If REFADJ is connected to AVCC through a 1kΩ resistor, the}
internal reference can be overdriven with an external source connected to REFIO. If REFADJ
is connected to AGND through a 1kΩ resistor, the internal reference is used to determine the
full-scale range of the data converter.
8
INP
Positive Analog Input Terminal
9
INN
Negative Analog Input Terminal
Clock Divider Input. This LVCMOS-compatible input controls which speed the converter’s
17
CLKDIV
digital outputs are updated. CLKDIV has an internal pulldown resistor.
CLKDIV = 0: ADC updates digital outputs at one-half the input clock rate.
CLKDIV = 1: ADC updates digital outputs at the input clock rate.
22
CLKP
True Clock Input. This input requires an LVDS-compatible input level to maintain the
converter’s excellent performance.
23
CLKN
Complementary Clock Input. This input requires an LVDS-compatible input level to maintain
the converter’s excellent performance.
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