MAX1123 Datasheet, PDF (10/17 Pages) Maxim Integrated Products – 1.8V, 10-Bit, 210Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications

1.8V, 10-Bit, 210Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
CLKP
CLKN
INP
INN
CLKDIV
CLOCK-
DIVIDER
CONTROL
INPUT
BUFFER
2.2kΩ
2.2kΩ
COMMON-MODE
BUFFER
Figure 1. MAX1123 Block Diagram
CLOCK
MANAGEMENT
T/H
10-BIT PIPELINE
QUANTIZER CORE
LVDS
DATA PORT
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REFERENCE
REFIO REFADJ
MAX1123
DCLKP
DCLKN
D0P/N–D9P/N
ORP
ORN
INP
2.2kΩ
AV_CC
INN
2.2kΩ
TO COMMON-MODE INPUT
TO COMMON-MODE INPUT
AGND
Figure 2. Simplified Analog Input Architecture
ADC FULL-SCALE = REFT - REFB
REFT
REFB
REFERENCE-
SCALING
AMPLIFIER
G
REFERENCE
BUFFER
REFIO
0.1µF
1V
CONTROL LINE TO
DISABLE REFERENCE
BUFFER
REFADJ
1kΩ
Detailed Description—Theory
of Operation
The MAX1123 uses a fully differential, pipelined archi-
tecture that allows for high-speed conversion, opti-
mized accuracy and linearity, while minimizing power
consumption and die size.
Both positive (INP) and negative/complementary analog
input terminals (INN) are centered around a common-
mode voltage of 1.4V, and accept a differential analog
input voltage swing of ±0.3125V each, resulting in a typi-
cal differential full-scale signal swing of 1.25V_P-P.
INP and INN are buffered prior to entering each track-
and-hold (T/H) stage and are sampled when the differ-
ential sampling clock signal transitions high. A 2-bit ADC
following the first T/H stage then digitizes the signal, and
controls a 2-bit digital-to-analog converter (DAC).
Digitized and reference signals are then subtracted,
AV_CC
AV_CC / 2
Figure 3. Simplified Reference Architecture
resulting in a fractional residue signal that is amplified
before it is passed on to the next stage through another
T/H amplifier. This process is repeated until the applied
input signal has successfully passed through all stages
of the 10-bit quantizer. Finally, the digital outputs of all
stages are combined and corrected for in the digital cor-
rection logic to generate the final output code. The result
is a 10-bit parallel digital output word in user-selectable
two’s complement or binary output formats with LVDS-
compatible output levels. See Figure 1 for a more
detailed view of the MAX1123 architecture.
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