DS1020S-15 Datasheet, PDF (8/9 Pages) Maxim Integrated Products – Programmable 8-Bit Silicon Delay Line

DS1020
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
t_WI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
t_RISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
t_FALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
t_PLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of the output pulse.
t_PHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of the output pulse.
TIMING DIAGRAM: NON-LATCHED PARALLEL MODE (S = 1, E = 1) Figure 6
TIMING DIAGRAM: LATCHED PARALLEL MODE (S=1) Figure 7
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