DS33Z41 Datasheet, PDF (70/167 Pages) Maxim Integrated Products – Quad IMUX Ethernet Mapper

DS33Z41 Quad IMUX Ethernet Mapper
Register Name:
Register Description:
Register Address:
GL.RTCAL
Global Receive and Transmit Serial Port Clock Activity Latched Status
04h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
RLCALS1
—
—
—
TLCALS1
Default
0
0
0
0
0
0
0
0
Bit 4: Receive Serial Interface Clock Activity Latched Status 1 (RLCALS1). This bit is set to 1 if the receive
clock for Serial Interface 1 has activity. This bit is cleared upon read.
Bit 0: Transmit Serial Interface Clock Activity Latched Status 1 (TLCALS1). This bit is set to 1 if the transmit
clock for Serial Interface 1 has activity. This bit is cleared upon read.
Register Name:
Register Description:
Register Address:
GL.SRCALS
Global SDRAM Reference Clock Activity Latched Status
05h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
REFCLKS SYSCLS
Default
0
0
0
0
0
0
0
0
Bit 1: Reference Clock Activity Latched Status (REFCLKS). This bit is set to 1 if REF_CLK has activity. This
bit is cleared upon read.
Bit 0: System Clock Input Latched Status (SYSCLS). This bit is set to 1 if SYSCLKI has activity. This bit is
cleared upon read.
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