MAX144_05 Datasheet, PDF (7/16 Pages) Maxim Integrated Products – +2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin μMAX

+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
DOUT
6k
C_L
GND
a) HIGH-Z TO V_0H, V_0L TO V_0H, AND V_OH TO HIGH-Z
Figure 1. Load Circuits for Enable and Disable Time
_______________Detailed Description
The MAX144/MAX145 analog-to-digital converters
(ADCs) use a successive-approximation conversion
(SAR) technique and on-chip track-and-hold (T/H)
structure to convert an analog signal to a serial 12-bit
digital output data stream.
This flexible serial interface provides easy interface to
microprocessors (µPs). Figure 2 shows a simplified
functional diagram of the internal architecture for both
the MAX144 (2 channels, single-ended) and the MAX145
(1 channel, pseudo-differential).
Analog Inputs: Single-Ended (MAX144)
and Pseudo-Differential (MAX145)
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit of
Figure 3. In single-ended mode (MAX144), both chan-
nels CH0 and CH1 are referred to GND and can be
connected to two different signal sources. Following the
power-on reset, the ADC is set to convert CH0. After
CH0 has been converted, CH1 will be converted and
the conversions will continue to alternate between
channels. Channel switching is performed by toggling
the CS/SHDN pin. Conversions can be performed on
the same channel by toggling CS/SHDN twice between
conversions. If only one channel is required, CH0 and
CH1 may be connected together; however, the output
data will still contain the channel identification bit
(before the MSB).
For the MAX145, the input channels form a single differ-
ential channel pair (CH+, CH-). This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side IN- must remain stable
within ±0.5LSB (±0.1LSB for optimum results) with
respect to GND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN- to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C_HOLD. The
acquisition interval spans from when CS/SHDN falls to
the falling edge of the second clock cycle (external
V_DD
6k
DOUT
C_L
GND
b) HIGH-Z TO V_0L, V_0H TO V_0L, AND V_OL TO HIGH-Z
CS/SHDN
SCLK
CONTROL
LOGIC
INTERNAL
CLOCK
OUTPUT ^DOUT
REGISTER
CH0
(CH+)
CH1
(CH-)
ANALOG
INPUT
MUX
(2 CHANNEL)
SCLK
12-BIT
T/H
IN SAR OUT
ADC
MAX144
MAX145
REF
( ) ARE FOR MAX145
Figure 2. Simplified Functional Diagram
REF
CH0
(CH+)
CH1
(CH-)
12-BIT CAPACITIVE DAC
MAX144
MAX145
INPUT
MUX
C_HOLD
16pF
ZERO
COMPARATOR
TO SAR
C_SWITCH
R_IN
9kΩ
TRACK
HOLD
GND
T/H
CONTROL LOGIC
SINGLE-ENDED MODE: CH0, CH1 = IN+; GND = IN-
DIFFERENTIAL-ENDED MODE: CH+ = IN+; CH- = IN-
( ) ARE FOR MAX145
Figure 3. Analog Input Channel Structure
clock mode) or from when CS/SHDN falls to the first
falling edge of SCLK (internal clock mode). At the end
of the acquisition interval, the T/H switch opens, retain-
ing charge on C_HOLD as a sample of the signal at IN+.
The conversion interval begins with the input multiplex-
er switching C_HOLD from the positive input (IN+) to the
negative input (IN-). This unbalances node ZERO at the
comparator’s positive input.
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