MAX144_05 Datasheet, PDF (10/16 Pages) Maxim Integrated Products – +2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin μMAX

+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
Table 1. Serial Output Data Stream for Internal and External Clock Mode
SCLK CYCLE
DOUT (Internal Clock)
DOUT (External Clock)
12
EOC 1
11
3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 CHID D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 CHID D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
External Reference
An external reference is required for both the MAX144
and the MAX145. At REF, the DC input resistance is a
minimum of 18kΩ. During a conversion, a reference
must be able to deliver 250µA of DC load current and
have an output impedance of 10Ω or less. Use a 0.1µF
bypass capacitor for best performance. The reference
input structure allows a voltage range of 0 to V_DD +
50mV, although noise levels will decrease effective res-
olution at lower reference voltages.
Automatic Power-Down Mode
Whenever the MAX144/MAX145 are not selected
(CS/SHDN = V_DD), the parts enter their shutdown
mode. In shutdown all internal circuitry turns off, reduc-
ing supply current to typically less than 0.2µA. With an
external reference stable to within 1LSB, the wake-up
time is 2.5µs. If the external reference is not stable with-
in 1LSB, the wake-up time must be increased to allow
the reference to stabilize.
__________Applications Information
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
error only and results directly from the ADC’s resolution
(N bits):
SNR_(MAX) = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. Therefore, SNR is computed by taking the ratio of
the RMS signal to the RMS noise which includes all
spectral components minus the fundamental, the first
five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is the ratio of the fundamental input frequency’s
RMS amplitude to RMS equivalent of all other ADC out-
put signals:
SINAD(dB)
=
20 x log



SIGNAL_RMS
(Noise + Distortion)_RMS



Effective Number of Bits (ENOB)
ENOB indicates the global accuracy of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists only of quantization noise. With an
input range equal to the full-scale range of the ADC, the
effective number of bits can be calculated as follows:
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first five harmon-
ics of the input signal to the fundamental itself. This is
expressed as:


THD = 20 x log ^




V
22
+ V32
+ V42
+ V52





V₁


where V₁ is the fundamental amplitude, and V₂ through
V₅ are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the fundamental
(maximum signal component) to the RMS value of the
next largest spurious component, excluding DC offset.
Connection to Standard Interfaces
The MAX144/MAX145 interface is fully compatible with
SPI, QSPI, and MICROWIRE standard serial interfaces.
If a serial interface is available, establish the CPU’s seri-
al interface as master so that the CPU generates the
serial clock for the MAX144/MAX145. Select a clock fre-
quency from 100kHz to 2.17MHz (external clock mode).
1) Use a general-purpose I/O line on the CPU to pull
CS/SHDN low while SCLK is low.
2) Wait for the minimum wake-up time (t_WAKE) speci-
fied before activating SCLK.
3) Activate SCLK for a minimum of 16 clock cycles.
The serial data stream of three leading ones, the
channel identification, and the MSB of the digitized
input signal begin at the first falling clock edge.
DOUT transitions on SCLK’s falling edge and is
available in MSB-first format. Observe the SCLK to
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