MAX1151 Datasheet, PDF (7/8 Pages) Maxim Integrated Products – 8-Bit, 750Msps Flash ADC

8-Bit, 500Msps Flash ADC
Operation
The MAX1151 has 255 preamplifier/comparator pairs;
each is supplied with the voltage from VRT to VRB,
divided equally by the resistive ladder as shown in the
Functional Diagram. This voltage is applied to the posi-
tive input of each preamplifier/comparator pair. An ana-
log input voltage applied at VIN is connected to the
negative inputs of each preamplifier/comparator pair.
The comparators are then clocked through each one’s
individual clock buffer. When the CLK pin is in the low
state, the master or input stage of the comparators
compares the analog input voltage to the respective
reference voltage. When CLK changes from low to
high, the comparators are latched to the state prior to
the clock transition and output logic codes in sequence
from the top comparators, closest to VRT (0V), down to
the point where the magnitude of the input signal
changes sign (thermometer code). The output of each
comparator is then registered into four 64-to-6 bit de-
coders when CLK is changed from high to low. At the
output of the decoders is a set of four 7-bit latches that
are enabled (track) when the clock changes from high
to low. From here, the output of the latches is coded
into six LSBs from four columns, and four columns are
coded into two MSBs. Finally, eight ECL output latches
and buffers are used to drive the external loads. The
conversion takes one clock cycle from the input to the
data outputs.
N
N+1
VIN
1.3ns
N+4
N+3
N+2
N+5
N+6
N+7
CLK
NCLK
DRA
NDRA
1.4ns
TYP
DATA BANK A
N-2
N
1.75ns
TYP
DRB
NDRB
DATA BANK B
1.4ns
TYP
N-1
1.75ns
TYP
N+2
N+4
N+1
N+3
Figure 2. Timing Diagram
INPUT CIRCUIT
AGND
OUTPUT CIRCUIT
CLOCK INPUT
AGND
AGND
DGND
VIN
V_R
CLK
NCLK
DATA OUT
V_EE
V_EE
Figure 3. Subcircuit Schematics
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