MAX1151 Datasheet, PDF (5/8 Pages) Maxim Integrated Products – 8-Bit, 750Msps Flash ADC

8-Bit, 750Msps Flash ADC
The MAX1151 has true differential analog and digital
data paths from the preamplifiers to the output buffers
(current-mode logic) for reducing potential missing
codes while rejecting common-mode noise.
Signature errors are also reduced by careful layout of the
analog circuitry. The device’s output drive capability can
provide full ECL swings into 50Ω loads.
Typical Interface Circuit
The circuit of Figure 1 shows a method of achieving the
least error by correcting for integral linearity, input-
induced distortion, and power-supply/ground noise. This
is achieved with the use of external reference-ladder tap
connections, an input buffer, and supply decoupling.
Contact the factory for the MAX1150/MAX1151 evalua-
tion kit manual, which contains more details on interfac-
ing the MAX1151. The function of each pin and external
connections to other components are described in the fol-
lowing sections.
VEE, AGND, DGND
V_EE is the supply pin with AGND as ground for the
device. The power-supply pins should be bypassed as
close to the device as possible with at least a 0.01µF
ceramic capacitor. A 1µF tantalum can also be used for
low-frequency suppression. DGND is the ground for the
ECL outputs, and should be referenced to the output
pulldown voltage and appropriately bypassed, as shown
in Figure 1.
VIN (Analog Input)
There are two analog input pins that are tied to the same
point internally. Either one may be used as an analog
input sense, while the other is used for input force. This is
convenient for testing the source signal to see if there is
sufficient drive capability. The pins can also be tied to-
gether and driven by the same source. The MAX1151 is
superior to similar devices due to a preamplifier stage
before the comparators. This makes the device easier to
drive because it has constant capacitance and induces
less slew-rate distortion.
CLK, NCLK (Clock Inputs)
The clock inputs are designed to be driven differentially
with ECL levels. The duty cycle of the clock should be
kept at 50%, to avoid causing larger second harmonics.
If this is not important to the intended application, duty
cycles other than 50% may be used.
D0 to D8, DR, NDR (A and B)
The digital outputs can drive 50Ω to ECL levels when
pulled down to -2V. When pulled down to -5.2V, the out-
puts can drive 130Ω to 1kΩ loads. All digital outputs are
gray code, with the coding as shown in Table 1.
Table 1. Output Coding
V_IN (V)
D8
0
1
-0.5
0
-1.0
0
-1.5
0
-2.0
0
D7 . . . D0
10000000
10000001
10000011
•
•
•
10100001
10100000
11100000
•
•
•
11000001
11000000
01000000
•
•
•
01100001
01100000
00100000
•
•
•
00000011
00000001
00000000
VRBF, VRBS, VRTF, VRTS, VRM
(Reference Inputs)
There are two reference inputs and one external refer-
ence voltage tap. These are -2V (VRB force and sense),
mid-tap (VRM), and AGND (VRT force and sense). The
reference pins and tap can be driven by op amps (as
shown in Figure 1), or VRM can be bypassed for limited
temperature operation. These voltage inputs can be by-
passed to AGND for further noise suppression, if
desired.
Thermal Management
The typical thermal impedance (θ_CA) for the MQUAD
package has been measured at θ_{CA = 17°C/W, in still}
air with no heatsink.
To ensure rated performance, we highly recommend
using this device with a heatsink that can provide ade-
quate air flow. We have found that a Thermalloy 17846
heatsink with a minimum air flow of 1 meter/second
(200 linear feet per minute) provides adequate thermal
performance under laboratory tests. Application-specif-
ic conditions should be taken into account to ensure
that the device is properly heat sinked.
_______________________________________________________________________________________ 5