MAX1132 Datasheet, PDF (7/19 Pages) Maxim Integrated Products – 16-Bit ADC, 200ksps, 5V Single-Supply with Reference

16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
Typical Operating Characteristics (continued)
(MAX1132/MAX1133: AV_DD = DV_DD = +5V , f_SCLK = 4.8MHz, external clock (50% duty cycle), 24 clocks/conversion (200ksps),
bipolar input, external REF = +4.096V, 0.22µF bypassing on REFADJ, 2.2µF on REF, 1µF on CREF, T_A = 25°C, unless otherwise noted.)
120
110
100
90
80
70
60
50
40
30
20
10
0
0.1
SFDR PLOT
f_SAMPLE = 200kHz
1
10
100
FREQUENCY (kHz)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0.1
THD PLOT
f_SAMPLE = 200kHz
1
10
100
FREQUENCY (kHz)
Pin Description
PIN
NAME
FUNCTION
Reference Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In
1
REF
internal reference mode, the reference buffer provides a +4.096V nominal output, externally adjustable at
REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to AV_DD. Bypass to
AGND with a 2.2µF capacitor when using the internal reference.
2
REFADJ ^{Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to AGND with 0.22µF. When using an}
external reference, connect REFADJ to AV_DD to disable the internal bandgap reference.
3
AGND Analog Ground. This is the primary analog ground (Star Ground).
4
AV_DD
Analog Supply. 5V ±5%. Bypass AV_DD to AGND (pin 3) with a 0.1µF capacitor.
5
DGND Digital Ground
6
SHDN Shutdown Control Input. Drive SHDN low to put the ADC in shutdown mode.
7
P2
User-Programmable Output 2
8
P1
User-Programmable Output 1
9
P0
User-Programmable Output 0
Serial Strobe Output. In internal clock mode, SSTRB goes low when the ADC begins a conversion and goes
10
SSTRB high when the conversion is finished. In external clock mode, SSTRB pulses high for one clock period
before the MSB decision. It is high impedance when CS is high in external clock mode.
11
DOUT
Serial Data Output. MSB first, straight binary format for unipolar input, two’s complement for bipolar input.
Each bit is clocked out of DOUT at the falling edge of SCLK.
12
RST
Reset Input. Drive RST low to put the device in the power-on default mode. See the Power-On Reset section.
_______________________________________________________________________________________ 7