MAX1132 Datasheet, PDF (5/19 Pages) Maxim Integrated Products – 16-Bit ADC, 200ksps, 5V Single-Supply with Reference

16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
TIMING CHARACTERISTICS (Figures 5 and 6)
(AV_DD = DV_DD = +5V ±5%, T_A = T_MIN to T_MAX, unless otherwise noted.)
PARAMETER
Acquisition Time
DIN to SCLK Setup
DIN to SCLK Hold
SCLK to DOUT Valid
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Fall to SSTRB
CS Fall to SSTRB Enable
CS Rise to SSTRB Disable
SSTRB Rise to SCLK Rise
RST Pulse Width
SYMBOL
t_ACQ
t_DS
t_DH
t_DO
t_DV
t_TR
t_CSS
t_CSH
t_CH
t_CL
t_SSTRB
t_SDV
t_STR
t_SCK
t_RS
CONDITIONS
C_LOAD = 50pF
C_LOAD = 50pF
C_LOAD = 50pF
C_LOAD = 50pF, external clock mode
C_LOAD = 50pF, external clock mode
Internal clock mode
MIN TYP MAX UNITS
1.14
µs
50
ns
0
ns
70
ns
80
ns
80
ns
100
ns
0
ns
80
ns
80
ns
80
ns
80
ns
80
ns
0
ns
208
ns
Note 1: Tested at AV_DD = DV_DD = +5V, bipolar input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset
error have been nulled.
Note 3: Offset nulled.
Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period, clock has 50% duty cycle.
Includes the acquisition time.
Note 5: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 6: When an external reference has a different voltage than the specified typical value, the full scale of the ADC will scale
proportionally.
Note 7: Electrical characteristics are guaranteed from AV_DD(MIN) = DV_DD(MIN) to AV_DD(MAX) = DV_DD(MAX). For operations beyond
this range, see the Typical Operating Characteristics. For guaranteed specifications beyond the limits, contact the factory.
Note 8: Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage.
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