MAX1086_07 Datasheet, PDF (7/17 Pages) Maxim Integrated Products – 150ksps, 10-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23

150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
Pin Description
NAME
PIN _{MAX1086 MAX1088}
MAX1087 MAX1089
1
V_DD
V_DD
2
AIN1
AIN+
3
AIN2
AIN-
4
GND
GND
5
REF
REF
6
CNVST CNVST
7
DOUT
DOUT
8
SCLK
SCLK
—
EP*
—
*MAX1087 TDFN package only.
FUNCTION
Positive Supply Voltage. +2.7V to +3.6V (MAX1087/MAX1089); +4.75V to +5.25V
(MAX1086/MAX1088). Bypass with a 0.1µF capacitor to GND.
Analog Input Channel 1 (MAX1086/MAX1087) or Positive Analog Input (MAX1088/MAX1089)
Analog Input Channel 2 (MAX1086/MAX1087) or Negative Analog Input (MAX1088/MAX1089)
Ground
External Reference Voltage Input. Sets the analog voltage range. Bypass with a 0.1µF
capacitor to GND.
Conversion Start. A rising edge powers-up the IC and places it in track mode. At the falling
edge of CNVST, the device enters hold mode and begins conversion. CNVST also selects the
input channel (MAX1086/MAX1087) or input polarity (MAX1088/MAX1089).
Serial Data Output. DOUT transitions the falling edge of SCLK. DOUT goes low at the start of a
conversion and presents the MSB at the completion of a conversion. DOUT goes high-
impedance once data has been fully clocked out.
Serial Clock Input. Clocks out data at DOUT MSB first.
Exposed Pad. Connect the exposed pad to ground or leave unconnected.
Detailed Description
The MAX1086–MAX1089 analog-to-digital converters
(ADCs) use a successive-approximation conversion (SAR)
technique and an on-chip track-and-hold (T/H) structure to
convert an analog signal into a 10-bit digital result.
CNVST
SCLK
MAX1086–MAX1089 _OSCILLATOR
INPUT SHIFT
REGISTER
CONTROL
AIN1
(AIN+)
AIN2
(AIN-)
REF
10-BIT
T/H
SAR
ADC
( ) ARE FOR MAX1088/MAX1089
Figure 3. Simplified Functional Diagram
DOUT
The serial interface provides easy interfacing to micro-
processors (µPs). Figure 3 shows the simplified internal
structure for the MAX1086/MAX1087 (2–channels, sin-
gle-ended) and the MAX1088/MAX1089 (1–channel,
true-differential).
True-Differential Analog Input Track/Hold
The equivalent circuit of Figure 4 shows the
MAX1086–MAX1089’s input architecture which is com-
posed of a T/H, input multiplexer, comparator, and
switched-capacitor DAC. The T/H enters its tracking
mode on the rising edge of CNVST. The positive input
capacitor is connected to AIN1 or AIN2 (MAX1086/
MAX1087) or AIN+ (MAX1088/MAX1089). The negative
input capacitor is connected to GND (MAX1086/
MAX1087) or AIN- (MAX1088/MAX1089). The T/H enters
its hold mode on the falling edge of CNVST and the dif-
ference between the sampled positive and negative
input voltages is converted. The time required for the T/H
to acquire an input signal is determined by how quickly
its input capacitance is charged. If the input signal’s
source impedance is high, the acquisition time length-
ens, and CNVST must be held high for a longer period of
time. The acquisition time, t_ACQ, is the maximum time
needed for the signal to be acquired, plus the power-up
time. It is calculated by the following equation:
t_ACQ = 7 x (R_S + R_IN) x 24pF + t_PWR
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