DS4830_1110 Datasheet, PDF (7/29 Pages) Maxim Integrated Products – Optical Microcontroller

DS4830
Optical Microcontroller
3-WIRE DIGITAL INTERFACE SPECIFICATION
(V_DD = 3.0V to 3.6V, T_A = -40NC to +85NC, unless otherwise noted.) (See Figure 2.)
PARAMETER
SYMBOL
CONDITIONS
MCL Clock Frequency
MCL Duty Cycle
MDIO Setup Time
MDIO Hold Time
MCS Pulse-Width Low
MCS Leading Time Before the
First MCL Edge
f_SCLOUT
t_3WDC
t_DS
t_DH
t_CSW
t_L
MCS Trailing Time After the Last
MCL Edge
t_T
MDIO, MCL Load
C_B3W Total bus capacitance on one line
MIN TYP MAX UNITS
833
kHz
50
%
100
ns
100
ns
500
ns
500
ns
500
ns
10
pF
SPI DIGITAL INTERFACE SPECIFICATION
(V_DD = 3.0V to 3.6V, T_A = -40NC to +85NC, unless otherwise noted.) (See Figure 3 and Figure 4.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
SPI Master Operating Frequency
SPI Slave Operating Frequency
SPI I/O Rise/Fall Time
MSPICK Output Pulse-Width
High/Low
1/t_MSPICK
1/t_SSPICK
t_{SPI_RF}
C_L = 15pF, pullup = 560I
t_MCH, t_MCL
MSPIDO Output Hold After
MSPICK Sample Edge
t_MOH
MSPIDO Output Valid to MSPICK
Sample Edge (MSPIDO Setup)
t_MOV
MSPIDI Input Valid to MSPICK
Sample Edge (MSPIDI Setup)
t_MIS
t_MSPICK/2
- t_{SPI_RF}
t_MSPICK/2
- t_{SPI_RF}
t_MSPICK/2
- t_{SPI_RF}
2t_{SPI_RF}
MSPIDI Input to MSPICK Sample
Edge Rise/Fall Hold
t_MIH
0
MSPICK Inactive to MSPIDO
Inactive
SSPICK Input Pulse-Width High/
Low
t_MLH
t_SCH, t_SCL
t_MSPICK/2
- t_{SPI_RF}
t_SCL/2
SSPICS Active to First Shift Edge
t_SSE
SSPIDI Input to SSPICK Sample
Edge Rise/Fall Setup
t_SIS
t_{SPI_RF}
t_{SPI_RF}
SSPIDI Input from SSPICK
Sample Edge Transition Hold
t_SIH
t_{SPI_RF}
SSPIDO Output Valid After
SSPICK Shift Edge Transition
t_SOV
MAX
f_SYS/2
f_SYS/4
25
2t_{SPI_RF}
UNITS
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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