DG441CJ Datasheet, PDF (7/8 Pages) Maxim Integrated Products – Improved, Quad, SPST Analog Switches

Improved, Quad, SPST Analog Switches
______________________________________________Timing Diagrams/Test Circuits
LOGIC +3V
INPUT
0V
SWITCH
OUTPUT
0V
t_f < 20ns
50%
t_r < 20ns
VOUT
tOFF
0.8 x VOUT
0.8 x VOUT
tON
LOGIC INPUT WAVEFORM IS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
Figure 2. Switching Time
SWITCH
INPUT
V_D
LOGIC
INPUT
+3V
+15V
V+
D
IN
GND
DG441
DG442
S
RL
V-
-15V
VOUT
35pF
REPEAT TEST FOR CHANNELS 2, 3, AND 4.
CL (INCLUDES FIXTURE AND STRAY CAPACITANCE)
( ) ^{VOUT = VD}
R_L
R_L + rDS(ON)
VOUT
IN
DG441
OFF
ON
∆VOUT
OFF
+15V
V+
RGEN
S
DG441
DG442
D
VOUT
VGEN
CL
GND IN
V-
1nF
OFF
ON
OFF
IN
DG442
Q = ∆VOUT × CL
Figure 3. Charge Injection
-15V
VIN = +3V
SIGNAL
GENERATOR 10dBm
RGEN = 50Ω
NETWORK
ANALYZER
RL
10nF ^+15V
V+
D
DG441
DG442
S
GND
IN
0.8V or 2.4V
V-
10nF
-15V
SIGNAL
GENERATOR 10dBm
RGEN = 50Ω
0.8V or 2.4V
NETWORK
ANALYZER
RL
10nF ^+15V
V+
D
DG441
DG442
S
50Ω
IN1
S
GND
IN2
D
V-
0.8V or 2.4V
10nF
-15V
Figure 4. Off-Isolation Rejection Ratio
Figure 5. Crosstalk (repeat for channels 3 and 4)
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