DG411 Datasheet, PDF (7/12 Pages) Vishay Siliconix – Precision Monolithic Quad SPST CMOS Analog Switches

Improved, Quad,
SPST Analog Switches
______________________________________________Timing Diagrams/Test Circuits
+3V
LOGIC
INPUT _0V
50%
tr < 20ns
tf < 20ns
SWITCH _0V
OUTPUT
t_OFF
V_OUT
0.9 x V_OUT
t_ON
0.9 x V_OUT
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
Figure 2. Switching-Time
SWITCH
INPUT
+5V
V_L
S1
IN1
+15V
V+
D1
DG411
DG412
DG413
SWITCH OUTPUT
V_OUT
R_L
C_L
300Ω
35pF
LOGIC
INPUT
GND
V-
0V
-15V
REPEAT TEST FOR IN AND S, FOR LOAD
CONDITIONS, SEE Electrical Characteristics.
C_L INCLUDES FIXTURE AND STRAY CAPACITANCE.
( ) ^VOUT ^{= V}S
R_L
R_L + R_DS(ON)
LOGIC +3V
INPUT
0V
SWITCH
OUTPUT 1
(VO1)
0V
SWITCH
OUTPUT 2
(VO2)
0V
50%
0.9 x VOUT1
0.9 x VOUT2
tD
tD
Figure 3. DG413 Break-Before-Make
V_S1 = +10V
V_S2 = +10V
+5V
S1 ^VL
S2
+15V
V+
D1
D2
DG413
V_OUT2 R_L1
V_OUT1
C_L1
LOGIC
INPUT
IN
R_L2
C_L2
GND
V-
-15V
R_L = 300Ω
C_L INCLUDES FIXTURE AND STRAY CAPACITANCE. ^{CL = 35pF}
VOUT
IN
OFF
ΔVOUT
OFF
ON
ON
OFF
OFF
IN
Q = (ΔVOUT)(CL)
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
Figure 4. Charge-Injection
VGEN
+5V
V_L
R_GEN
S
+15V
V+
D
GND
IN
V-
-15V
V_IN = +3V
DG411
DG412
DG413
VOUT
CL
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