MAX1338 Datasheet, PDF (6/24 Pages) Maxim Integrated Products – 14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC

14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
ELECTRICAL CHARACTERISTICS (continued)
(AV_DD = DV_DD = +5.0V, DRV_DD = +3.0V, AGND = DGND = DRGND = 0, INTCLK/EXTCLK = AGND, f_CLK = 5MHz, input range =
±10V, REFP2 = REFP1, REFN2 = REFN1, COM1 = COM2, 1.0nF from REFADC to AGND, 1.0µF and 0.1µF from COM1 to AGND,
0.1µF from REFP1 to AGND, 0.1µF from REFN1 to AGND, 1.0µF from REFP1 to REFN1. Typical values are at T_A = +25°C. T_A = T_MIN
to T_MAX, unless otherwise noted.)
PARAMETER
EOC Fall to RD Fall Setup Time
EOLC Fall to RD Fall Setup Time
Input Data Setup Time
Input Data Hold Time
External CLK Period
External CLK High Period
External CLK Low Period
External Clock Frequency
Internal Clock Frequency
CONVST High to CLK Edge
Quiet Time
SYMBOL
t_EOCRD
t_EOLCRD
t_DTW
t_WTD
t_CLK
t_CLKH
t_CLKL
f_CLK
f_INT
t_CNTC
t_QUIET
CONDITIONS
Logic sensitive to rising edges
Logic sensitive to rising edges
(Note 4)
MIN TYP MAX UNITS
0
ns
0
ns
10
ns
10
ns
166
200
ns
60
ns
60
ns
1
6
MHz
5.0
5.25
5.5
MHz
30
ns
600
ns
Note 1: See definition for this parameter in the Definitions section.
Note 2: Differential reference voltage (REFP–REFN) error nulled.
Note 3: This is the load the MAX1338 presents to an external reference at REFADC.
Note 4: Minimum CLK frequency is limited only by the internal T/H droop rate. Limit the time between the rising edge of CONVST to
the falling edge of EOLC to a maximum of 0.25ms.
1.6mA
TO OUTPUT PIN
50pF
1.6V
0.8mA
Figure 1. Load Circuit for Data Access Time and Bus-
Relinquish Time
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