MAX1338 Datasheet, PDF (5/24 Pages) Maxim Integrated Products – 14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC

14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
ELECTRICAL CHARACTERISTICS (continued)
(AV_DD = DV_DD = +5.0V, DRV_DD = +3.0V, AGND = DGND = DRGND = 0, INTCLK/EXTCLK = AGND, f_CLK = 5MHz, input range =
±10V, REFP2 = REFP1, REFN2 = REFN1, COM1 = COM2, 1.0nF from REFADC to AGND, 1.0µF and 0.1µF from COM1 to AGND,
0.1µF from REFP1 to AGND, 0.1µF from REFN1 to AGND, 1.0µF from REFP1 to REFN1. Typical values are at T_A = +25°C. T_A = T_MIN
to T_MAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
TIMING CHARACTERISTICS (Figures 4, 5, and 6)
Internal clock
Time to First Conversion Result
t_{EOC1 External clock}
Time to Subsequent Conversions
t_NEXT
Internal clock
External clock
CONVST Pulse-Width Low
CS Pulse Width
RD Pulse-Width Low
RD Pulse-Width High
WR Pulse-Width Low
CS to WR Setup Time
WR to CS Hold Time
CS to RD Setup Time
RD to CS Hold Time
Data Access Time
(RD Low to Valid Data)
t_CONVST
t_CS
t_RDL
t_RDH
t_WRL
t_CTW
t_WTC
t_CTR
t_RTC
Internal clock
External clock
t_ACC Figure 1
MIN TYP MAX UNITS
2.9
3.2
3.5
µs
16
CLK
Cycles
600
ns
3
CLK
Cycles
0.2
µs
0.1
30
ns
30
ns
30
ns
30
ns
0
ns
0
ns
0
ns
0
ns
30
ns
Bus Relinquish Time
(RD High to D_ High-Z)
t_REQ Figure 1
5
30
ns
CLK Rise to End-of-Conversion
(EOC) Rise/Fall Delay
t_EOCD
20
ns
CLK Rise to End-of-Last-
Conversion (EOLC) Fall Delay
CONVST Rise to EOLC Fall Delay
EOC Pulse-Width Low
t_EOLCD
t_CVEOLCD
t_EOC
Internal clock
External clock
Wake-Up Time From Standby
Wake-Up Time From Shutdown
All bypass capacitors discharged
20
20
180
200
1
7
5
ns
ns
ns
CLK
Cycle
µs
ns
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