MAX1193EVKIT Datasheet, PDF (6/13 Pages) Maxim Integrated Products – MAX1193 Evaluation Kit

MAX1193 Evaluation Kit
Digital Output Format
The MAX1193 features a single 8-bit, multiplex CMOS-
compatible digital output bus. Channel A is available at
the output during A/ B high. Channel B is available at
the output during A/ B low. The channel selection signal
(A/ B) is an image of the clock that may be used to syn-
chronize the output data. Refer to the MAX1193 data
sheet for more information.
A driver is used to buffer the ADC’s digital outputs. This
buffer is able to drive large capacitive loads, which
may be present at the logic analyzer connection, with-
out compromising the digital output signals. The out-
puts of the buffers are connected to header J1 located
on the right side of the EV kit, where the user can con-
nect a logic analyzer or data-acquisition system. See
Table 4 for channel and bit locations on header J1.
All even-number pins on header J1 are connected to
OGND.
Table 4. Header J1 Output Bit Location (Multiplexed Output Operation)
CHANNEL
A/B
BIT D0
A
(CLK )*
1
J1-3
A0
B
(CLK )*
0
J1-3
B0
*Trigger signal for the logic analyzer.
BIT D1
J1-5
A1
J1-5
B1
BIT D2
J1-7
A2
J1-7
B2
BIT D3
J1-9
A3
J1-9
B3
BIT D4
J1-13
A4
J1-13
B4
BIT D5
J1-15
A5
J1-15
B5
BIT D6
J1-17
A6
J1-17
B6
BIT D7
J1-19
A7
J1-19
B7
6 _______________________________________________________________________________________