DG401 Datasheet, PDF (6/8 Pages) Intersil Corporation – Monolithic CMOS Analog Switches

Improved, Dual, High-Speed Analog Switches
______________________________________________Timing Diagrams/Test Circuits
LOGIC
+3V
INPUT
0V
SWITCH
OUTPUT
0V
tr < 20ns
50%
tf < 20ns
VOUT
tOFF
0.9 x VOUT
tON
VOUT
0.9 x VOUT
LOGIC INPUT WAVEFORM IS INVERTED FOR
SWITCHES THAT HAVE THE OPPOSITE LOGIC
SENSE CONTROL.
Figure 2. Switching Time
+5V
V_D = +10V (for tON)
V_D = -10V (for tOFF)
VL
D
IN
+15V
V+
S
RL = 1000Ω
CL = 35pF
VOUT
DG401
DG403
DG405
LOGIC
GND
V-
INPUT
0V
-15V
REPEAT TEST FOR IN2 AND S2
( ) ^{VOUT = V}D
RL
RL + r_DS(ON)
FOR LOAD CONDITIONS, SEE Electrical Characteristics.
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
LOGIC +3V
INPUT
0V
SWITCH
OUTPUT 1
0V
50%
VOUT1
0.9 x VOUT
SWITCH
VOUT2
OUTPUT 2
0V
tD
0.9 x VOUT
tD
Figure 3. Break-Before-Make Interval
∆VOUT
VOUT
IN
ON
OFF
ON
Q = (∆VOUT) (CL)
+5V
VL
+10V ^D
+10V ^D
IN
LOGIC
GND
INPUT
+15V
V+
S
DG401
DG403
DG405
VOUT1
S
VOUT2 _RL1
CL1
RL2
V-
CL2
0V
-15V
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
RL = 1000Ω
CL = 35pF
RGEN
+5V
V_L
S
VGEN
GND
0V
+15V
V+
D
V-
-15V
DG401
DG403
DG405
VOUT
CL
10nF
Figure 4. Charge Injection
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