MAX1586A Datasheet, PDF (5/32 Pages) Maxim Integrated Products – High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones

High-Efficiency, Low-I_Q PMICs with
Dynamic Core for PDAs and Smart Phones
ELECTRICAL CHARACTERISTICS (continued)
(V_IN = 3.6V, V_BKBT = 3.0V, V_LBI = 1.1V, V_DBI = 1.35V, circuit of Figure 5, T_A = 0°C to +85°C, unless otherwise noted. Typical values
are at T_A = +25°C.)
PARAMETER
LBI Threshold (Falling)
DBI Threshold (Falling)
RSO Threshold (Falling)
RSO Deassert Delay
LBI Input Bias Current
DBI Input Bias Current
Thermal-Shutdown Temperature
Thermal-Shutdown Hysteresis
LOGIC INPUTS AND OUTPUTS
LBO, DBO, POK, RSO, SDA Output
Low Level
LBO, DBO, POK, RSO Output Low
Level
CONDITIONS
MAX1586 hysteresis is
5% (typ)
LBI = IN (for preset)
With resistors at LBI
MAX1586 hysteresis is
5% (typ)
DBI = IN (for preset)
With resistors at LBI
Voltage on REG7, hysteresis is 5% (typ)
MAX1586
MAX1586
T_J rising
2.6V ≤ V7 ≤ 5.5V, sinking 1mA
V7 = 1V, sinking 100µA
MIN
3.51
0.98
3.024
1.208
2.25
61
-50
TYP
3.6
1.00
3.15
1.232
2.41
65.5
-5
15
+160
15
MAX
3.69
1.02
3.276
1.256
2.56
70
50
UNITS
V
V
V
ms
nA
nA
°C
°C
0.4
V
0.4
V
LBO, DBO, POK, RSO Output-High
Leakage Current
Pin = 5.5V
0.2
µA
ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input High Level
2.6V ≤ V_IN ≤ 5.5V
1.6
V
ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input Low Level
2.6V ≤ V_IN ≤ 5.5V
0.4
V
ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input Leakage Current
Pin = GND, 5.5V
1
1
µA
SERIAL INTERFACE
Clock Frequency
400 kHz
Bus-Free Time Between START and
STOP
1.3
µs
Hold Time Repeated START Condition
CLK Low Period
CLK High Period
Setup Time Repeated START Condition
DATA Hold Time
DATA Setup Time
0.6
µs
1.3
µs
0.6
µs
0.6
µs
0
µs
100
ns
Maximum Pulse Width of Spikes that
Must be Suppressed by the Input
Filter of Both DATA and CLK Signals
50
ns
Setup Time for STOP Condition
0.6
µs
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