MAX14945 Datasheet, PDF (5/21 Pages) Maxim Integrated Products – 2.75kVRMS Isolated 500kbps Half-Duplex RS-485

MAX14945
2.75kV_RMS Isolated 500kbps Half-Duplex RS-485/
RS-422 Transceiver with ±30kV ESD Protection
Switching Electrical Characteristics
(V_DDA – V_GNDA = 1.71V to 5.5V, V_DDB – V_GNDB = 4.5V to 5.5V, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at
V_DDA – V_GNDA = 3.3V, V_DDB – V_GNDB = 5V, V_GNDA = V_GNDB, and T_A = +25°C.) (Note 7)
PARAMETER
DYNAMIC
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS
Common Mode Transient
Immunity
CMTI
(Note 8)
35
kV/μs
Glitch Rejection
TXD, DE, RXD
10
17
29
ns
DRIVER
Driver Propagation Delay
Differential Driver Output Skew
|tDPLH - tDPHL|
tDPLH, tDPHL
RL = 54Ω, C_L = 50pF, Figure 2 and
Figure 3
tDSKEW
RL = 54Ω, C_L = 50pF, Figure 2 and
Figure 3
1040
ns
144
ns
Driver Differential Output Rise
or Fall Time
tLH, tHL
R_L = 54Ω, C_L = 50pF, Figure 2 and
Figure 3
900
ns
Maximum Data Rate
DRMAX
500
kbps
Driver Enable to Output High
tDZH
RL = 500Ω, C_L = 50pF, Figure 4
2540
ns
Driver Enable to Output Low
Driver Disable Time from Low
Driver Disable Time from High
RECEIVER
tDZL
tDLZ
tDHZ
RL = 500Ω, C_L = 50pF, Figure 5
RL = 500Ω, C_L = 50pF, Figure 5
RL = 500Ω, C_L = 50pF, Figure 4
2540
ns
140
ns
140
ns
Receiver Propagation Delay
tRPLH, tRPHL CL = 15pF, Figure 6 and 7 (Note 9)
240
ns
Receiver Output Skew
|tRPLH - tRPHL|
tRSKEW
CL = 15pF, Figure 6 and 7
(Note 9)
34
ns
Maximum Data Rate
DRMAX
500
Receiver Enable to Output High
tRZH
RL = 1kΩ, C_L = 15pF, S2 closed,
Figure 8
Receiver Enable to Output Low
tRZL
RL = 1kΩ, C_L = 15pF, S1 closed,
Figure 8
Receiver Disable Time From Low
tRLZ
RL = 1kΩ, C_L = 15pF, S1 closed,
Figure 8
kbps
20
ns
30
ns
20
ns
Receiver Disable Time From High
tRHZ
RL = 1kΩ, C_L = 15pF, S2 closed,
Figure 8
20
ns
Note 2: All devices are 100% production tested at T_A = +25°C. Specifications over temperature are guaranteed by design.
Note 3: All currents into the device are positive. All currents out of the device are negative. All voltages are referenced to their
respective ground (GNDA or GNDB), unless otherwise noted.
Note 4: V_LDO max indicates voltage capability of the circuit. Power dissipation requirements may limit V_LDO max to a lower value.
Note 5: ΔV_OD and ΔV_OC are the changes in V_OD and V_OC, respectively, when the TXD input changes state.
Note 6: The short circuit output current applies to the peak current just prior to foldback current limiting.
Note 7: Not production tested. Guaranteed by design.
Note 8: CMTI is the maximum sustainable common-mode voltage slew rate while maintaining the correct output states. CMTI
applies to both rising and falling common-mode voltage edges. Tested with the transient generator connected between
GNDA and GNDB.
Note 9: Capacitive load includes test probe and fixture capacitance.
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