MAX1446-07 Datasheet, PDF (5/22 Pages) Maxim Integrated Products – 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference

10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(V_DD = 3.0V, OV_DD = 2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; V_REFIN = 2.048V, REFOUT connected
to REFIN through a 10kΩ resistor, V_IN = 2V_P-P (differential with respect to COM), C_L ≈ 10pF at digital outputs, f_CLK = 62.5MHz
(50% duty cycle), T_A = T_MIN to T_MAX, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design
and characterization. Typical values are at T_A = +25°C.)
PARAMETER
POWER REQUIREMENTS
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
Output Supply Current
Power-Supply Rejection
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
OE Fall to Output Enable
OE Rise to Output Disable
CLK Pulse Width High
SYMBOL
CONDITIONS
V_DD
OV_DD
I_VDD
I_OVDD
PSRR
C_L = 10pF
Operating, f_IN = 19.943MHz at -0.5dBFS
Shutdown, clock idle, PD = OE = OV_DD
Operating, C_L = 15pF, f_IN = 19.943MHz at
-0.5dBFS
Shutdown, clock idle, PD = OE = OV_DD
Offset
Gain
t_DO
t_ENABLE
t_DISABLE
Figure 5 (Note 3)
Figure 5
Figure 5
t_CH
Figure 6, clock period 16ns
MIN TYP MAX UNITS
2.7
3.0
3.6
V
1.7
3.0
3.6
V
30
37
mA
4
15
µA
7
mA
1
20
µA
± 0.1
mV/V
± 0.1
%/V
5
8
ns
10
ns
1.5
ns
8.3
± 2.5
ns
CLK Pulse Width Low
t_CL
Figure 6, clock period 16ns
8.3
± 2.5
ns
Wake-Up Time
t_WAKE (Note 4)
1.5
µs
Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a 1.024V full-scale
input voltage range.
Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB better, if referenced to the two-tone envelope.
Note 3: Digital outputs settle to V_IH, V_IL.
Note 4: With R_EFIN driven externally, REFP, COM, and REFN are left floating while powered down.
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