MAX125_08 Datasheet, PDF (5/15 Pages) Maxim Integrated Products – 2x4-Channel, Simultaneous-Sampling 14-Bit DAS

2x4-Channel, Simultaneous-Sampling
14-Bit DAS
TIMING CHARACTERISTICS (Figure 4)
(AV_DD = +5V, AV_SS = -5V, DV_DD = +5V, AGND = DGND = 0V, T_A = T_MIN to T_MAX, unless otherwise noted.)
PARAMETER
CONVST Pulse Width
CS to WR Setup Time
CS to WR Hold Time
WR Low Pulse Width
CS to CONVST Delay
Address Setup Time
Address Hold Time
RD to INT Delay
Delay Time Between Reads
CS to RD Setup Time
CS to RD Hold Time
RD Low Pulse Width
Data-Access Time
Bus-Relinquish Time
Conversion Time
Conversion Rate/Channel
Start-Up Time
SYMBOL
t_CW
t_CWS
t_CWH
t_WR
t_CSD
t_AS
t_AH
t_ID
t_RD
t_CRS
t_CRH
t_RD
t_DA
t_DH
t_CONV
CONDITIONS
25pF load
25pF load (Note 13)
25pF load (Note 14)
Mode 1, 1 channel
Mode 2, 2 channel
Mode 3, 3 channel
Mode 4, 4 channel
Mode 1, 1 channel
Mode 2, 2 channel
Mode 3, 3 channel
Mode 4, 4 channel
Exiting shutdown
MIN TYP
30
0
0
30
125
30
0
40
0
0
30
5
5
MAX
30
30
45
3
6
9
12
250
142
100
76
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ksps
µs
Note 1: AV_DD = +5V, AV_SS = -5V, DV_DD = +5V, V_REFIN = 2.500V (external), V_IN = ±5V (MAX125) or ±2.5V (MAX126).
Note 2: Relative accuracy is the analog value’s deviation at any code from its theoretical value after the full-scale range has been
calibrated.
Note 3: CLK synchronized with CONVST.
Note 4: f_IN = 10.06kHz, V_IN = ±5V (MAX125) or ±2.5V (MAX126).
Note 5: First five harmonics.
Note 6: All inputs except CH1A driven with ±5V (MAX125) or ±2.5V (MAX126) 10kHz signal; CH1A connected to AGND and digitized.
Note 7: Guaranteed by design. Not production tested.
Note 8: AV_DD = +5V, AV_SS = -5V, DV_DD = +5V, V_IN = 0V (all channels).
Note 9: Temperature drift is defined as the change in output voltage from +25°C to T_MIN or T_MAX. It is calculated as
TC = [∆REFOUT/REFOUT] / ∆T.
Note 10: See Figure 2.
Note 11: Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage. Tested with one input
at full scale and all others at AGND. V_REFIN = 2.5V (internal).
Note 12: Tested with V_IN = AGND on all channels, V_REFIN = 2.5V (internal).
Note 13: The data-access time is defined as the time required for an output to cross 0.8V or 2.0V. It is measured using the circuit of
Figure 1. The measured number is then extrapolated back to determine the value with a 25pF load.
Note 14: The bus-relinquish time is derived from the measured time taken for the data outputs to change 0.5V when loaded with the
circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging/discharging the 120pF
capacitor. Thus, the time given is the part’s true bus-relinquish time, independent of the external bus loading capacitance.
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