MAX1236 Datasheet, PDF (5/22 Pages) Maxim Integrated Products – 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
TIMING CHARACTERISTICS (Figure 1) (continued)
(V_DD = 2.7V to 3.6V (MAX1237/MAX1239), V_DD = 4.5V to 5.5V (MAX1236/MAX1238), V_REF = 2.048V (MAX1237/MAX1239), V_REF =
4.096V (MAX1236/MAX1238), C_REF = 0.1µF, f_SCL = 1.7MHz, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at
T_A = +25°C, see Tables 1–5 for programming notation.)
PARAMETER
SYMBOL
CONDITIONS
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (C_B = 400pF, Note 11)
Serial Clock Frequency
f_SCLH (Note 12)
Hold Time, Repeated START
Condition (Sr)
t_{HD, STA}
MIN TYP MAX UNITS
1.7
MHz
160
ns
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated START
Condition (Sr)
t_LOW
t_HIGH
t_SU, _STA
320
ns
120
ns
160
ns
Data Hold Time
Data Setup Time
Rise Time of SCL Signal
(Current Source Enabled)
t_HD, _DAT (Note 10)
t_SU, _DAT
t_RCL
0
150
ns
10
ns
20
80
ns
Rise Time of SCL Signal after
Acknowledge Bit
t_RCL1 Measured from 0.3V_DD - 0.7V_DD
20
160
ns
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for STOP (P) Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
t_FCL
t_RDA
t_FDA
t_SU, _STO
C_B
t_SP
Measured from 0.3V_DD - 0.7V_DD
Measured from 0.3V_DD - 0.7V_DD
Measured from 0.3V_DD - 0.7V_DD
(Notes 10 and 12)
20
80
ns
20
160
ns
20
160
ns
160
ns
400
pF
0
10
ns
Note 1: For DC accuracy, the MAX1136/MAX1138 are tested at V_DD = 5V and the MAX1137/MAX1139 are tested at V_DD = 3V. All
devices are configured for unipolar, single-ended inputs.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 3: Offset nulled.
Note 4: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 5: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 6: The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to V_DD.
Note 7: When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11) decouple AIN_/REF to GND with a
0.01µF capacitor.
Note 8: ADC performance is limited by the converter’s noise floor, typically 300µV_P-P.
Note 9: Measured as for the MAX1237/MAX1239
[ ] ^
 V_FS(3.6V) − V_FS(2.7V)

×
2^N
−
1^

V_{REF }
(3.6V − 2.7V)
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