MAX108 Datasheet, PDF (5/32 Pages) Maxim Integrated Products – ±5V, 1.5Gsps, 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier

±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
AC ELECTRICAL CHARACTERISTICS (continued)
(V_CCA = V_CCI = V_CCD = +5.0V, V_EE = -5.0V, V_CCO = +3.3V, REFIN connected to REFOUT, f_S = 1.5Gsps, f_IN at -1dBFS, T_A = +25°C,
unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
TIMING CHARACTERISTICS
Maximum Sample Rate
Clock Pulse Width Low
Clock Pulse Width High
Aperture Delay
Aperture Jitter
f_MAX
t_PWL
t_PWH
t_AD
t_AJ
Figure 17
Figure 17
Figure 4
Figure 4
1.5
0.3
0.3
100
<0.5
Gsps
ns
5
ns
ps
ps
Reset Input Data Setup Time
(Note 13)
t_SU
Figure 15
0
ps
Reset Input Data Hold Time
(Note 13)
t_HD
Figure 15
0
ps
CLK to DREADY Propagation
Delay
t_PD1 Figure 17
2.2
ns
DREADY to DATA Propagation
Delay (Note 14)
t_PD2 Figure 17
-50
150
350
ps
DATA Rise Time
DATA Fall Time
DREADY Rise Time
DREADY Fall Time
Primary Port Pipeline
Delay
Auxiliary Port Pipeline
Delay
t_RDATA
t_FDATA
t_RDREADY
t_FDREADY
t_PDP
t_PDA
20% to 80%, C_L = 3pF
20% to 80%, C_L = 3pF
20% to 80%, C_L = 3pF
20% to 80%, C_L = 3pF
Figures 6, 7, 8
DIV1, DIV2 modes
DIV4 mode
Figures 6, 7, 8
DIV1, DIV2 modes
DIV4 mode
420
ps
360
ps
220
ps
180
ps
7.5
Clock
7.5
Cycles
8.5
Clock
9.5
Cycles
Note 1: Static linearity parameters are computed from a “best-fit” straight line through the code transition points. The full-scale
range (FSR) is defined as 256 times the slope of the line.
Note 2: The offset control input is a self-biased voltage divider from the internal +2.5V reference voltage. The nominal open-circuit
voltage is +1.25V. It may be driven from an external potentiometer connected between REFOUT and GNDI.
Note 3: The clock input’s termination voltage can be operated between -2.0V and GNDI. Observe the absolute maximum ratings
on the CLK+ and CLK- inputs.
Note 4: Input logic levels are measured with respect to the V_CCO power-supply voltage.
Note 5: All PECL digital outputs are loaded with 50Ω to V_CCO - 2.0V. Measurements are made with respect to the V_CCO power-
supply voltage.
Note 6: The current in the V_CCO power supply does not include the current in the digital output’s emitter followers, which is a func-
tion of the load resistance and the V_TT termination voltage.
Note 7: Common-mode rejection ratio (CMRR) is defined as the ratio of the change in the transfer-curve offset voltage to the
change in the common-mode voltage, expressed in dB.
Note 8: Power-supply rejection ratio (PSRR) is defined as the ratio of the change in the transfer-curve offset voltage to the change
in power-supply voltage, expressed in dB.
Note 9: Measured with the positive supplies tied to the same potential; V_CCA = V_CCD = V_CCI. V_CC varies from +4.75V to +5.25V.
Note 10: V_EE varies from -5.25V to -4.75V.
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