MAX108 Datasheet, PDF (22/32 Pages) Maxim Integrated Products – ±5V, 1.5Gsps, 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier

±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
Reset Output
Finally, the reset signal is presented in differential PECL
format to the last block of the reset signal path.
RSTOUT+/RSTOUT- output the time-aligned reset sig-
nal, used for resetting additional external demuxes in
applications that need further output data-rate reduc-
tion. Many demux devices require their reset signal to
be asserted for several clock cycles while they are
clocked. To accomplish this, the MAX108 DREADY
clock will continue to toggle while RSTOUT is asserted.
When a single MAX108 device is used, no synchroniz-
ing reset is required because the order of the samples
in the output ports is unchanged, regardless of the
phase of the DREADY clock. In DIV2 mode, the data in
the auxiliary port is delayed by 8.5 clock cycles, while
the data in the primary port is delayed by 7.5 clock
cycles. The older data is always in the auxiliary port,
regardless of the phase of the DREADY clock.
The reset output signal, RSTOUT, is delayed by one
fewer clock cycles (6.5 clock cycles) than the primary
port. The reduced latency of RSTOUT serves to mark
the start of synchronized data in the primary and auxil-
iary ports. When the RSTOUT signal returns to a zero,
the DREADY clock phase is reset.
Since there are two possible phases of the DREADY
clock with respect to the input clock, there are two pos-
sible timing diagrams to consider. The first timing dia-
gram (Figure 18) shows the RSTOUT timing and data
alignment of the auxiliary and primary output ports
when the DREADY clock phase is already reset. For
this example, the RSTIN pulse is two clock cycles long.
Under this condition, the DREADY clock continues
uninterrupted, as does the data stream in the auxiliary
and primary ports.
The second timing diagram (Figure 19) shows the
results when the DREADY phase is opposite from the
reset phase. In this case, the DREADY clock “swallows”
a clock cycle of the sample clock, resynchronizing to
the reset phase. Note that the data stream in the auxil-
iary and primary ports has reversed. Before reset was
ADC SAMPLE NUMBER
CLK- n
n+1
n+2
n+3
CLK
CLK+
RESET
INPUT
t_SU
RSTIN-
RSTIN+
DREADY-
DREADY
DREADY+
AUXILIARY
DATA PORT
PRIMARY
DATA PORT
RESET OUT
DATA PORT
RSTOUT-
RSTOUT+
ADC SAMPLES ON THE RISING EDGE OF CLK+
n+4
n+5
n+6
n+7
n+8
n+9
t_HD
n-1
n
n+10 n+11
n+1
n+2
n+12 n+13
n+3
n+4
NOTE: THE LATENCY TO THE RESET OUTPUT IS 6.5 CLOCK CYCLES. THE LATENCY TO THE PRIMARY PORT IS 7.5 CLOCK CYCLES, AND
THE LATENCY TO THE AUXILIARY PORT IS 8.5 CLOCK CYCLES. ALL DATA PORTS ARE UPDATED ON THE RISING EDGE OF THE DREADY+ CLOCK.
Figure 18. Reset Output Timing in Demuxed DIV2 Mode (DREADY Aligned)
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