DS1646-120 Datasheet, PDF (5/13 Pages) Maxim Integrated Products – Nonvolatile Timekeeping RAM

DS1646/DS1646P
CLOCK ACCURACY (DIP MODULE)
The DS1646 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require
additional calibration. For this reason, methods of field clock calibration are not available and not
necessary. Clock accuracy is also affected by the electrical environment and caution should be taken to
place the RTC in the lowest level EMI section of the PCB layout. For additional information refer to
Application Note 58.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1646 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within ±1.53 minutes per month (35 ppm) at 25°C. Clock
accuracy is also affected by the electrical environment and caution should be taken to place the RTC in
the lowest level EMI section of the PCB layout. For additional information refer to Application Note 58.
1646 REGISTER MAP—BANK1 Table 2
ADDRESS _B7
B₆
B₅
DATA
B₄
B₃
B₂
B₁
B₀
1FFFF
——— — — — — —
FUNCTION
Year
00–99
1FFFE
XXX —————
Month 01–12
1FFFD
XX
-
—————
Date
01–31
1FFFC
X FT X
X
X
———
Day
01–07
1FFFB
X X——————
Hour
00–23
1FFFA
X — — — — — — — Minutes 00–59
1FFF9 _OSC — — — — — — — Seconds 00–59
1FFF8
WR X
X
X
X
X
X
Control
A
OSC = Stop Bit
W = Write Bit
R = Read Bit
X = Unused
FT = Frequency Test
Note: All indicated “X” bits are unused but must be set to “0” during write cycles to ensure proper clock
operation.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1646 is in the read mode whenever WE (write enable) is high; CE (chip enable) is low. The
device architecture allows ripple-through access to any of the address locations in the NVSRAM. Valid
data will be available at the DQ pins within t_AA after the last address input is stable, providing that the CE
and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be
available at the latter of chip-enable access (t_CEA) or at output enable access time (t_OEA). The state of the
data input/output pins (DQ) is controlled by CE and OE . If the outputs are activated before t_AA, the data
lines are driven to an intermediate state until t_AA. If the address inputs are changed while CE and OE
remain valid, output data will remain valid for output data hold time (t_OH) but will then go indeterminate
until the next address access.
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