DS34T101 Datasheet, PDF (49/74 Pages) Maxim Integrated Products – Single/Dual/Quad/Octal TDM-Over-Packet Chip

_____________________________________________________ DS34T101/DS34T102/DS34T104/DS34T108
11. JTAG Information
For the latest JTAG model search under www.maxim-ic.com/tools/bsdl/.
11.1 JTAG Description
The DS34T108 supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional
public instructions included are HIGHZ, CLAMP and IDCODE. See Figure 11-1 for a JTAG block diagram. The
DS34T108 contains the following items that meet the requirements set by the IEEE 1149.1 Standard Test Access
Port and Boundary Scan Architecture:
Test Access Port (TAP)
TAP Controller
Instruction Register
Bypass Register
Boundary Scan Register
Device Identification Register
The Test Access Port has the necessary interface pins, namely JTCLK, JTRST, JTDI, JTDO, and JTMS. Details on
these pins can be found in Section 10.2. Details on the Boundary Scan Architecture and the Test Access Port can
be found in IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
Figure 11-1. JTAG Block Diagram
Vdd
10K
BOUNDRY SCAN
REGISTER
IDENTIFICATION
REGISTER
BYPASS
REGISTER
INSTRUCTION
REGISTER
TEST ACCESS PORT
CONTROLLER
Vdd
Vdd
10K
10K
MUX
SELECT
OUTPUT ENABLE
JTDI
JTMS JTCLK JTRST
JTDO
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