DS34T101 Datasheet, PDF (1/74 Pages) Maxim Integrated Products – Single/Dual/Quad/Octal TDM-Over-Packet Chip

Rev: 072707
DS34T101/DS34T102/DS34T104/DS34T108
Single/Dual/Quad/Octal TDM-Over-Packet Chip
General Description
The IETF PWE³ SAToP/CESoPSN/TDMoIP/HDLC
draft-compliant DS34T108 allows up to eight T1/E1
links or frame-based serial HDLC links to be
transported transparently through a switched IP or
MPLS packet network. Jitter and wander of
recovered clocks conform to G.823/G.824, G.8261,
and TDM specifications. This eliminates the need for
remote timing sources in cabinets and pedestals.
The Ethernet side of the DS34T108 provides high
QoS capabilities to its MII/RMII/SSMII port, while the
WAN side supports full-featured T1/E1 framers and
LIUs. This takes the solution all the way through
analog, while preserving options to make use of TDM
streams at key intermediate points. The high level of
integration that the DS34T108 brings minimizes cost,
board space, and time to market.
Applications
TDM Circuit Extension Over PSN
o Leased—Line Services Over PSN
o TDM Over G/E—PON
o TDM Over Cable
o TDM Over WiMAX
Cellular Backhaul Over PSN
Multiservice Over Unified PSN
HDLC—Based Traffic Transport Over PSN
Functional Diagram
CPU
Bus
DS34T108
Octal
T1/E1/J1
Transceiver
Framers
BERT
& CAS
LIUs
Circuit
Emulation
Engine
10/100
Ethernet
xMII
MAC
CLAD
Buffer
Manager
TDM
Access
Clock Inputs
SDRAM
Interface
Features
♦ Full-Featured T1/E1/J1 LIU/Framer/TDM-Over-
Packet
♦ Supports Adaptive Clock Recovery, Common
Clock (Using RTP), External Clock, and
Loopback Timing Modes
♦ Selectable 32-Bit or 16-Bit Processor Bus
♦ Clock Rate Adapter for T1/E1 Master Clock
♦ 10/100 Ethernet MAC That Supports
MII/RMII/SSMII
♦ Fully Compatible with IEEE 802.3 Standard
♦ VLAN Support According to 802.1 p&Q
♦ Multiprotocol Encapsulation Supports IPv4,
IPv6, UDP, RTP, L2TPv3, MPLS, and Metro
Ethernet
♦ End-to-End TDM Synchronization Through
the IP/MPLS Domain by Eight Independent
On-Chip TDM Clock Recovery Mechanisms
♦ Single Serial Support for RS-530 and V.35
♦ Single DS3/E3/STS-1 to Ethernet
♦ Packet Loss Compensation and Handling of
Misordered Packets
♦ 64 Independent Bundle/Connections
♦ Glueless SDRAM Buffer Management
♦ 1.8V Core, 3.3V I/O
♦ Complies with IETF PWE3 RFCs and Drafts
for CESoPSN, SAToP, TDMoIP, and HDLC
Features continued in Section 7.
Ordering Information
PART
PORTS TEMP RANGE
DS34T108GN
8
-40°C to +85°C
DS34T108GN+
8
-40°C to +85°C
DS34T104GN*
4
-40°C to +85°C
DS34T104GN+*
4
-40°C to +85°C
DS34T102GN*
2
-40°C to +85°C
DS34T102GN+*
2
-40°C to +85°C
DS34T101GN*
1
-40°C to +85°C
DS34T101GN+*
1
-40°C to +85°C
+Denotes a lead-free package.
*Future product—Contact factory for availability.
PIN-
PACKAGE
484 HSBGA
484 HSBGA
484 TEBGA
484 TEBGA
484 TEBGA
484 TEBGA
484 TEBGA
484 TEBGA
Maxim Integrated Products 1
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about
device errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim
Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.