MAX3107_15 Datasheet, PDF (41/52 Pages) Maxim Integrated Products – SPI/I2C UART with 128-Word FIFOs

MAX3107
SPI/I²C UART with 128-Word FIFOs
PLLConfig—PLL Configuration Register
ADDRESS:
MODE:
BIT
NAME
RESET
7
PLLFactor1
0
0x1A
R/W
6
PLLFactor0
0
5
PreDiv5
0
4
PreDiv4
0
3
PreDiv3
0
2
PreDiv2
0
1
PreDiv1
0
0
PreDiv0
1
Bits 7 and 6: PLLFactor[1:0]
The two PLLFactor[1:0] bits allow programming the PLL’s multiplication factor. The input and output frequencies of the
PLL have to be limited to the ranges shown in Table 4. Enable the PLL through CLKSource[2].
Bits 5–0: PreDiv[5:0]
The six PreDiv[5:0] bits allow programming the divisor of the PLL’s predivider. The divisor must be chosen such that
the output frequency of the predivider, which equals the PLL’s input frequency, is limited to the ranges shown in Table 4. The
input frequency of XIN is f_CLK; f_PLLIN = f_CLK/PreDiv (Figure 4). PreDiv is an integer that must be in the range of 1 to 63.
f_CLK
PREDIVIDER ^fPLLIN
PLL
fREF
FRACTIONAL
BAUD-RATE
GENERATOR
Figure 14. PLL Signal Path
Table 4. PLLFactor[1:0] Selection Guide
PLLFactor1
0
0
1
1
PLLFactor0
0
1
0
1
MULTIPLICATION
FACTOR
6
48
96
144
f_PLLIN
MIN (kHz)
MAX
500
800kHz
850
1.2MHz
425
1MHz
390
667kHz
f_REF
MIN (MHz)
MAX (MHz)
3
4.8
40.8
56
40.8
96
56
96
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