MAX16064 Datasheet, PDF (4/52 Pages) Maxim Integrated Products – ±0.3% Accurate, Quad, Power-Supply Controller with Active-Voltage Output Control and PMBus Interface

±0.3% Accurate, Quad, Power-Supply Controller with
Active-Voltage Output Control and PMBus Interface
ELECTRICAL CHARACTERISTICS (continued)
(V_AVDD = V_DVDD = 3.0V to 3.6V, V_EN = 2V, V_{RS_+} - V_{RS_-} = 2V, V_{RS_-} = 0V, T_A = T_J = -40°C to +85°C, unless otherwise specified.
Typical values are at V_AVDD = V_DVDD = 3.3V, T_A = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
ADDRESS PINS (A1/SCLE, A2/SDAE, A3/CONTROL)
Input Logic-Low Voltage
0.3
V
Input Logic-Low Hysteresis
50
mV
Input Logic-High Voltage
V_AVDD
V
- 0.4
Input Logic-High Hysteresis
50
mV
Input Leakage Current
-12
+12
µA
SMBus INTERFACE (SCL, SDA) (Note 3)
SCL, SDA Input Low Voltage
SCL, SDA Input High Voltage
V_IL
Input voltage falling
V_IH
Input voltage rising
0.8
V
2.1
V
SCL, SDA Input Leakage Current
(Per Pin)
Device powered or unpowered, V_AVDD = 0V
-1
to 3.6V, V_SCL = V_SDA = 0 or V_AVDD
+1
µA
Input Capacitance
SCL, SDA Output Low Voltage
SMBUS TIMING
C_IN
V_OL
I_SINK = 3mA
10
pF
0.4
V
Serial-Clock Frequency
f_SCL
10
100
kHz
Bus Free Time Between STOP
and START Condition
t_BUF
4.7
µs
START Condition Setup Time
START Condition Hold Time
STOP Condition Setup Time
Clock Low Period
Clock High Period
Data Setup Time
Output Fall Time
Data Hold Time
Pulse Width of Spike Suppressed
SMBus Timeout
OTHER TIMING PARAMETERS
t_SU:STA
t_HD:STA
t_SU:STO
t_LOW
t_HIGH
t_SU:DAT
t_OF
t_HD:DAT
t_SP
t_TIMEOUT
C_BUS = 10pF to 400pF
From 50% SCL falling to SDA change
SMBCLK time low for reset
4.7
µs
4.0
µs
4.0
µs
4.7
µs
4.0
µs
250
ns
300
ns
300
ns
30
ns
25
55
ms
PMBus Command Response
Time
t_{PMB_RSP}
300
µs
Fault Response Time
t_{FAULT_RSP}
5
ms
Recovery Time After Device
Reset
t_{RST_WAIT}
15
µs
Note 2: 100% production tested at T_A = +25°C. Limits over temperature are guaranteed by design.
Note 3: The MAX16064 supports SCL clock stretching.
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