MAX16064 Datasheet, PDF (26/52 Pages) Maxim Integrated Products – ±0.3% Accurate, Quad, Power-Supply Controller with Active-Voltage Output Control and PMBus Interface

±0.3% Accurate, Quad, Power-Supply Controller with
Active-Voltage Output Control and PMBus Interface
The dual functionality of A3/CONTROL of the
MAX16064 requires that the system enable signal be
isolated from A3 until the address setting has been
read and latched by the MAX16064. Figure 11 shows
one implementation for the three possible states of the
A3/CONTROL setting. In each case, the system enable
signal (MAX16064_EN) is applied to the input of a
three-state buffer whose output is kept in the high-
impedance state by a control input signal (HIZ_EN) for
a time period during which the MAX16064 reads and
latches the A3/CONTROL address setting. After this
period, the control signal HIZ_EN goes low and allows
the system enable signal to be applied to the
MAX16064 A3/CONTROL pin. After a t_{A3_LOW}, the
MAX16064_EN signal transitions from low to high and
causes the MAX16064s to commence power-supply
startup operations.
PMBus Digital Interface
From a software perspective, the MAX16064 appears
as a PMBus device capable of executing a subset of
PMBus commands. A PMBus 1.0-compliant device
uses the SMBus version 1.1 for transport protocol and
responds to the SMBus slave address. In this data
sheet, the term SMBus is used to refer to the electrical
characteristics of the PMBus communication using the
SMBus physical layer. The term PMBus is used to refer
to the PMBus command protocol.
The MAX16064 employs five standard SMBus protocols
(Write Word, Read Word, Write Byte, Read Byte, and
Send Byte (see Figures 12–15)) to program output volt-
age and warning/faults thresholds, read monitored
data, and provide access to all manufacturer-specific
commands.
3.3V
MAX16064_EN
HIZ_EN
33kΩ
U1
MAX16064
A3
A2
A1
REFO
AVDD
REFO
1µF
HIZ_EN
MAX16064_UVLO
t_{RST_WAIT}
MAX16064
A3
MAX16064_EN
A2
A1
A3/CONTROL
U2
REFO
1µF
t_{A3_LOW}
33kΩ
U3
MAX16064
A3
A2
A1
REFO
HIZ_EN PLACES U1, U2, AND U3 OUTPUTS IN HIGH-IMPEDANCE STATE WHEN ASSERTED.
U1, U2, AND U3 ARE NOT NECESSARY IF AN EEPROM IS ATTACHED TO A1/SCLE
AND A2/SDAE. A1/SCLE, A2/SDAE ARE EITHER PULLED UP OR PULLED DOWN WITH
33kΩ WHEN CONNECTED TO AN EEPROM.
1µF
Figure 11. Application Diagram with A3/CONTROL as Both Address and On/Off Control Signal
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