MAX152 Datasheet, PDF (4/12 Pages) Maxim Integrated Products – +3V, 8-Bit ADC with 1uA Power-Down

+3V, 8-Bit ADC with 1µA Power-Down
TIMING CHARACTERISTICS
(Unipolar input range, V_DD = 3V, V_SS = 0V, T_A = +25°C, unless otherwise noted.) (Note 6)
PARAMETER SYMBOL CONDITIONS
ALL GRADES
T_A = +25°C
MIN TYP MAX
MAX152C/E
T_A = T_MIN to T_MAX
MIN MAX
Conversion Time
(WR-RD Mode)
Conversion Time
(RD Mode)
t_CWR
t_CRD
t_RD < t_INTL,
C_L = 100pF
1.8
2.06
2.0
2.3
Power-Up Time
CS to RD,WR
Setup Time
CS to RD,WR
Hold Time
CS to RDY
Delay
Data Access Time
(RD Mode) (Note 7)
RD to INT Delay
(RD Mode)
Data Hold Time
(Note 8)
t_UP
t_CSS
t_CSH
t_RDY
t_ACC0
t_INTH
t_DH
C_L = 50pF,
R_L = 5.1kΩ to V_DD
C_L = 100pF
C_L = 50pF
0.9
0
0
100
t_CRD
+100
100 160
100
1.2
0
0
120
t_CRD
+130
170
130
MAX152M
T_A = T_MIN to T_MAX UNITS
MIN MAX
2.4
µs
2.6
µs
1.4
µs
0
ns
0
ns
140
ns
t_CRD
+150
ns
180
ns
150
ns
Delay Time Between
Conversions
t_P
450
600
700
ns
WR Pulse Width
t_WR
Delay Time Between
WR and RD Pulses
t_RD
0.6
10
0.66 10
0.8
10
µs
0.8
0.9
1.0
µs
RD Pulse Width
t_READ1
WR-RD mode,
determined by t_ACC1 400
(Figure 6)
500
600
ns
Data Access Time
(Note 7)
t_ACC1
WR-RD mode,
t_RD < t_INTL, C_L = 100pF
(Figure 6)
400
500
600
ns
RD to INT Delay
WR to INT Delay
t_RI
t_INTL
C_L = 50pF
300
340
0.7 1.45
1.6
400
ns
1.8
µs
RD Pulse Width
WR-RD mode,
t_READ2
t_RD > t_INTL,
determined by t_ACC2
180
(Figure 5)
220
250
ns
Data Access Time
(Note 7)
WR to INT Delay
Data Access Time
After INT (Note 7)
t_ACC2
t_IHWR
t_ID
WR-RD mode,
t_RD < t_INTL , C_L = 100pF
(Figure 5)
Stand-alone mode,
C_L = 50pF
Stand-alone mode,
C_L = 100pF
180
220
180
200
100
130
250
ns
240
ns
150
ns
Note 6: Input control signals are specified with tr = tf = 5ns, 10% to 90% of +3.0V, and timed from a voltage level of 1.3V. Timing
delays get shorter at higher supply voltages. See the Converson Time vs. Supply Voltage graph in the Typical Operating
Characteristics to extrapolate timing delays at other power-supply voltages.
Note 7: See Figure 1 for load circuit. Parameter defined as the time required for the output to cross 0.66V or 2.0V.
Note 8: See Figure 2 for load circuit. Parameter defined as the time required for the data lines to change 0.5V.
4 _________________________________________________________________________________________