English
Language : 

MAX1480E Datasheet, PDF (4/19 Pages) Maxim Integrated Products – 15kV ESD-Protected, Isolated RS-485/RS-422
±15kV ESD-Protected, Isolated RS-485/RS-422
Data Interfaces
SWITCHING CHARACTERISTICS—MAX1480EA/MAX1490EA (continued)
(VCC_ = +5V ±10%, VFS = VCC_, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC_ = +5V and TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
|tPLH - tPHL| Differential
Receiver Skew
Maximum Data Rate
Time to Shutdown
Shutdown to Driver Output High
Shutdown to Driver Output Low
tSKD
fMAX
tSHDN
tZH(SHDN)
tZH(SHDN)
Figures 5 and 10, RDIFF = 54Ω, CL1 = CL2 = 100pF
tSKEW, tSKD, tPHL ≤ 25% of data period
2.5
Figures 6 and 9, CL = 100pF, S2 closed
Figures 6 and 9, CL = 100pF, S1 closed
30 150 ns
Mbps
100
µs
3
15
µs
3
15
µs
SWITCHING CHARACTERISTICS—MAX1480EC/MAX1490EB
(VCC_ = +5V ±10%, VFS = VCC_, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC_ = +5V and TA = +25°C.)
PARAMETER
Driver Input to Output
Propagation Delay
Driver Output Skew
Driver Rise or Fall Time
Driver Enable to Output High
(MAX1480EC Only)
SYMBOL
tPLH
tPHL
tSKEW
tR, tF
tZH
CONDITIONS
MIN
Figures 5 and 7, RDIFF = 54Ω, CL1 = CL2 = 100pF
Figures 5 and 7, RDIFF = 54Ω, CL1 = CL2 = 100pF
Figures 5 and 7, RDIFF = 54Ω, CL1 = CL2 = 100pF
Figures 5 and 7, RDIFF = 54Ω, CL1 = CL2 = 100pF
Figures 6 and 8, CL = 100pF, S2 closed
TYP MAX UNITS
1.4 3.0
µs
1.1 3.0
300 1200 ns
1.0
2.0
µs
1.4
4.5
µs
Driver Enable to Output Low
(MAX1480EC Only)
tZL
Figures 6 and 8, CL = 100pF, S1 closed
1.4
4.5
µs
Driver Disable Time from Low
(MAX1480EC Only)
tLZ
Figures 6 and 8, CL = 15pF, S1 closed
2.0
4.5
µs
Driver Disable Time from High
(MAX1480EC Only)
Receiver Input to Output
Propagation Delay
|tPLH - tPHL| Differential
Receiver Skew
tHZ
tPLH
tPHL
tSKD
Figures 6 and 8, CL = 15pF, S2 closed
Figures 5 and 10, RDIFF = 54Ω, CL1 = CL2 = 100pF
Figures 5 and 10, RDIFF = 54Ω, CL1 = CL2 = 100pF
1.7
4.5
µs
0.9 3.0
µs
1.1 3.0
200
ns
Maximum Data Rate
Time to Shutdown
Shutdown to Driver Output High
Shutdown to Driver Output Low
fMAX
tSHDN
tZH(SHDN)
tZL(SHDN)
tSKEW, tSKD ≤ 25% of data period
Figures 6 and 9, CL = 100pF, S2 closed
Figures 6 and 9, CL = 100pF, S1 closed
160
kbps
100
µs
3
15
µs
3
15
µs
Note 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to logic-
side ground (GND_), unless otherwise specified.
Note 2: For DE´ and DI´ pin descriptions, see Detailed Block Diagram and Typical Application Circuit (Figure 1 for MAX1480EA/
MAX1480EC, Figure 2 for MAX1490EA/MAX1490EB).
Note 3: Shutdown supply current is the current at VCC1 and VCC2 when shutdown is enabled.
Note 4: Limit guaranteed by applying 1520VRMS for 1s. Test voltage is applied between all pins on one side of the package to all
pins on the other side of the package, e.g., between pins 1–14 and pins 15–28 on the 28-pin package.
Note 5: Applies to peak current (see Typical Operating Characteristics). Although the MAX1480EA/MAX1480EC and
MAX1490EA/MAX1490EB provide electrical isolation between logic ground and signal paths, they do not provide isolation
between external shields and the signal paths (see Isolated Common Connection section).
4 _______________________________________________________________________________________