MAX1436B Datasheet, PDF (4/24 Pages) Maxim Integrated Products – Octal, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs

Octal, 12-Bit, 40Msps, 1.8V ADC
with Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V_AVDD = 1.8V, V_OVDD = 1.8V, V_CVDD = 3.3V, V_GND = 0V, external V_REFIO = 1.24V, C_REFIO = 0.1µF, C_REFP = 10µF, C_REFN = 10µF, f_CLK
= 40MHz (50% duty cycle), V_DT = 0V, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C.) (Notes 2, 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
COMMON-MODE OUTPUT (CMOUT)
CMOUT Output Voltage
V_CMOUT
CLOCK INPUT (CLK)
0.76
V
Input High Voltage
V_CLKH
Input Low Voltage
V_CLKL
Clock Duty Cycle
Clock Duty-Cycle Tolerance
Input Leakage Current
Input at GND
DI_{IN Input at AVDD}
Input Capacitance
DC_IN
DIGITAL INPUTS (PLL_, LVDSTEST, DT, SLVS, STBY, T/B)
0.8 x
V
V_AVDD
0.2 x
V
V_AVDD
50
%
±30
%
5
µA
80
5
pF
Input Logic-High Voltage
V_IH
0.8 x
V_AVDD
V
Input Logic-Low Voltage
V_IL
0.2 x
V_AVDD
V
Input Leakage Current
Input at GND
DI_{IN Input at AVDD}
5
µA
80
Input Capacitance
DC_IN
LVDS OUTPUTS (OUT_P, OUT_N), SLVS/LVDS = 0
5
pF
Differential Output Voltage
Output Common-Mode Voltage
V_OHDIFF R_TERM = 100Ω
V_OCM R_TERM = 100Ω
250
1.125
450
mV
1.375
V
Rise Time (20% to 80%)
t_RL
R_TERM = 100Ω, C_LOAD = 5pF
350
ps
Fall Time (80% to 20%)
t_FL
R_TERM = 100Ω, C_LOAD = 5pF
350
ps
SLVS OUTPUTS (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, FRAMEN), SLVS/LVDS = 1, DT = 1
Differential Output Voltage
Output Common-Mode Voltage
Rise Time (20% to 80%)
Fall Time (80% to 20%)
V_OHDIFF
V_OCM
t_RS
t_FS
R_TERM = 100Ω
R_TERM = 100Ω
R_TERM = 100Ω, C_LOAD = 5pF
R_TERM = 100Ω, C_LOAD = 5pF
205
mV
220
mV
320
ps
320
ps
STANDBY MODE (STBY)
STBY Fall to Output Enable
t_ENABLE
200
µs
STBY Rise to Output Disable
t_DISABLE
60
ns
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