MAX1436B Datasheet, PDF (12/24 Pages) Maxim Integrated Products – Octal, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs

Octal, 12-Bit, 40Msps, 1.8V ADC
with Serial LVDS Outputs
Pin Description (continued)
PIN
NAME
FUNCTION
58
FRAMEN
Negative Frame-Alignment LVDS/SLVS Output. A rising edge on the differential FRAME
output aligns to a valid D0 in the output data stream.
59
FRAMEP
Positive Frame-Alignment LVDS/SLVS Output. A rising edge on the differential FRAME output
aligns to a valid D0 in the output data stream.
61
CLKOUTN Negative LVDS/SLVS Serial Clock Output
62
CLKOUTP Positive LVDS/SLVS Serial Clock Output
65
OUT3N Channel 3 Negative LVDS/SLVS Output
66
OUT3P Channel 3 Positive LVDS/SLVS Output
68
OUT2N Channel 2 Negative LVDS/SLVS Output
69
OUT2P Channel 2 Positive LVDS/SLVS Output
72
OUT1N Channel 1 Negative LVDS/SLVS Output
73
OUT1P Channel 1 Positive LVDS/SLVS Output
78
OUT0N Channel 0 Negative LVDS/SLVS Output
79
OUT0P Channel 0 Positive LVDS/SLVS Output
LVDS Test Pattern Enable. Drive LVDSTEST high to enable the output test pattern (0000 1011
80
LVDSTEST 1101 MSB → LSB). As with the analog conversion results, the test pattern data is output LSB
first. Drive LVDSTEST low for normal operation.
Standby Input. An active-high level on STBY puts the MAX1436B into standby mode, leaving
81
STBY
the reference circuitry active. Drive STBY low for normal operation.
82
PLL3 PLL Control Input 3. See Table 1 for details.
83
PLL2 PLL Control Input 2. See Table 1 for details.
84
PLL1 PLL Control Input 1. See Table 1 for details.
85
T/B
Output Format-Select Input. Drive T/B high to select binary output format. Drive T/B low to
select two’s-complement output format.
Negative Reference Bypass Output. Connect a ≥ 1µF (10µF typ) capacitor between REFP and
90
REFN REFN, and connect a ≥ 1µF (10µF typ) capacitor between REFN and GND. Place the
capacitors as close as possible to the device on the same side of the PCB.
Positive Reference Bypass Output. Connect a ≥ 1µF (10µF typ) capacitor between REFP and
91
REFP REFN, and connect a ≥ 1µF (10µF typ) capacitor between REFP and GND. Place the
capacitors as close as possible to the device on the same side of the PCB.
Reference Input/Output. For internal reference operation (REFADJ = GND), the reference
93
REFIO output voltage is 1.24V. For external reference operation (REFADJ = AVDD), apply a stable
reference voltage at REFIO. Bypass to GND with ≥ 0.1µF.
Internal/External Reference-Mode-Select and Reference Adjust Input. For internal reference
94
REFADJ
mode, connect REFADJ directly to GND. For external reference mode, connect REFADJ
directly to AVDD. For reference-adjust mode, see the Full-Scale Range Adjustments Using the
Internal Reference section.
95
CMOUT
Common-Mode Reference Voltage Output. CMOUT outputs the input common-mode voltage
for DC-coupled applications. Bypass CMOUT to GND with ≥ 0.1µF capacitor.
97
IN0P Channel 0 Positive Analog Input
98
IN0N Channel 0 Negative Analog Input
—
EP
Exposed Pad. EP is internally connected to GND. Connect EP to GND.
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