MAX1418 Datasheet, PDF (4/20 Pages) Maxim Integrated Products – 15-Bit, 65Msps ADC with -78.2dBFS Noise Floor for IF Applications

15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
ELECTRICAL CHARACTERISTICS (continued)
(AV_CC = 5V, DV_CC = DRV_CC = 2.5V, GND = 0, INP and INN driven differentially with -2dBFS, CLKP and CLKN driven differentially
with a 2V_P-P sinusoidal input signal, C_L = 5pF at digital outputs, f_CLK = 65MHz, T_A = T_MIN to T_MAX, unless otherwise noted. Typical
values are at T_A = +25°C, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and char-
acterization.)
PARAMETER
Pipeline Latency
SYMBOL
t_LATENCY
CONDITIONS
MIN TYP MAX UNITS
3
Clock
cycles
CLKP Rising Edge to DATA
Not Valid
t_DNV (Note 3)
2.6
3.8
5.7
ns
CLKP Rising Edge to DATA
Valid (Guaranteed)
t_DGV (Note 3)
3.4
5.2
8.6
ns
DATA Setup Time
(Before DAV Rising Edge)
t_SETUP (Note 3)
t_CLKP - t_CLKP t_CLKP
0.5 + 1.3 + 2.4
ns
DATA Hold Time
(After DAV Rising Edge)
t_HOLD (Note 3)
TIMING CHARACTERISTICS (DV_CC = DRV_CC = 3.3V) Figure 4
CLKP/CLKN Duty Cycle
Duty cycle
Effective Aperture Delay
Output Data Delay
Data Valid Delay
Pipeline Latency
t_AD
t_DAT
t_DAV
(Note 3)
(Note 3)
t_LATENCY
t_CLKN - t_CLKN - t_CLKN -
ns
3.6
2.8
2.0
50
±5
%
230
ps
2.8
4.1
6.5
ns
5.3
6.3
8.6
ns
3
Clock
cycles
CLKP Rising Edge to
DATA Not Valid
t_DNV (Note 3)
2.5
3.4
5.2
ns
CLKP Rising Edge to
DATA Valid (Guaranteed)
t_DGV (Note 3)
3.2
4.4
7.4
ns
DATA Setup Time
(Before DAV Rising Edge)
t_SETUP (Note 3)
t_CLKP t_CLKP t_CLKP
ns
+ 0.2 + 1.7 + 2.8
DATA Hold Time
(After DAV Rising Edge)
t_HOLD (Note 3)
t_CLKN - t_CLKN - t_CLKN -
3.5
2.7
2.0
ns
POWER REQUIREMENTS
Analog Supply Voltage Range
Digital Supply Voltage Range
Output Supply Voltage Range
Analog Supply Current
AV_CC
DV_CC
DRV_CC
I_AVCC
(Note 2)
(Note 2)
5 ±3%
V
2.5 to 3.5
V
2.5 to 3.5
V
382 447
mA
Digital + Output Supply Current
I_DVCC +
DRV_CC
f_CLK = 65MHz, C_LOAD = 5pF
35.5
42
mA
Analog Power Dissipation
PDISS
2000
mW
Note 1: Dynamic performance is based on a 32,768-point data record with a sampling frequency of f_SAMPLE = 65.0117120MHz, an
input frequency of f_IN = f_SAMPLE x (35283/32768) = 70.001472MHz, and a frequency bin size of 1984Hz. Close-in (f_IN
±23.8kHz) and low-frequency (DC to 47.6kHz) bins are excluded from the spectrum analysis.
Note 2: Apply the same voltage levels to DV_CC and DRV_CC
Note 3: Guaranteed by design and characterization.
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