MAX1418 Datasheet, PDF (10/20 Pages) Maxim Integrated Products – 15-Bit, 65Msps ADC with -78.2dBFS Noise Floor for IF Applications

15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
PIN
1, 2, 3, 6, 9, 12, 14–17,
20, 23, 26, 27, 30, 52–56, EP
4
5
7, 8, 18, 19, 21, 22, 24, 25, 28
10
11
13
29
31, 41, 42, 51
32
33
34
35
36
37
38
39
40
43
44
45
46
47
48
49
50
Pin Description
NAME
GND
CLKP
CLKN
AV_CC
INP
INN
CM
DV_CC
DRV_CC
DOR
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
DAV
FUNCTION
Converter Ground. Analog, digital, and output driver grounds are internally
connected to the same potential. Connect the converter’s EP to GND.
Differential Clock, Positive Input Terminal
Differential Clock, Negative Input Terminal
Analog Supply Voltage. Provide local bypassing to ground with 0.1µF to 0.22µF
capacitors.
Differential Analog Input, Positive Terminal
Differential Analog Input, Negative/Complementary Terminal
Common-Mode Reference Terminal
Digital Supply Voltage. Provide local bypassing to ground with 0.1µF to 0.22µF
capacitors.
Digital Output Driver Supply Voltage. Provide local bypassing to ground with
0.1µF to 0.22µF capacitors.
Data Overrange Bit. This control line flags an overrange condition in the ADC.
If DOR transitions high, an overrange condition was detected. If DOR remains low,
the ADC operates within the allowable full-scale range.
Digital CMOS Output Bit 0 (LSB)
Digital CMOS Output Bit 1
Digital CMOS Output Bit 2
Digital CMOS Output Bit 3
Digital CMOS Output Bit 4
Digital CMOS Output Bit 5
Digital CMOS Output Bit 6
Digital CMOS Output Bit 7
Digital CMOS Output Bit 8
Digital CMOS Output Bit 9
Digital CMOS Output Bit 10
Digital CMOS Output Bit 11
Digital CMOS Output Bit 12
Digital CMOS Output Bit 13
Digital CMOS Output Bit 14 (MSB)
Data Valid Output. This output can be used as a clock control line to drive an
external buffer or data-acquisition system. The typical delay time between the
falling edge of the converter clock and the rising edge of DAV is 6.5ns.
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