MAX1162_10 Datasheet, PDF (4/18 Pages) Maxim Integrated Products – 16-Bit, +5V, 200ksps ADC with 10μA Shutdown

16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
ELECTRICAL CHARACTERISTICS (continued)
(AV_DD = DV_DD = +4.75V to +5.25V, f_SCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), V_REF = +4.096V, C_REF = 4.7µF,
T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C.)
PARAMETER
POWER SUPPLIES
Analog Supply
Digital Supply
Analog Supply Current
Digital Supply Current
SYMBOL
CONDITIONS
AV_DD
DV_DD
I_AVDD CS = DGND
I_DVDD
CS = DGND,
DOUT = all
zeros
200ksps
100ksps
10ksps
1ksps
200ksps
100ksps
10ksps
1ksps
MIN TYP MAX UNITS
4.75
5.25
V
2.7
5.25
V
2.75 3.25
1.4
mA
0.14
0.014
0.6
1.0
0.3
mA
0.03
0.003
Shutdown Supply Current
I_AVDD +
I_DVDD
CS = DV_DD, SCLK = idle
0.1
10
µA
Power-Supply Rejection Ratio
PSRR ^{AVDD = DVDD = +4.75V to +5.25V, full-scale}
68
dB
input (Note 5)
TIMING CHARACTERISTICS (Figures 1, 2, 3, and 6)
(AV_DD = DV_DD = +4.75V to +5.25V, f_SCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), V_REF = +4.096V, T_A = T_MIN
to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C.)
PARAMETER
Acquisition Time
SCLK to DOUT Valid
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS Pulse Width
CS Fall to SCLK Rise Setup
CS Rise to SCLK Rise Hold
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Period
SYMBOL
t_ACQ
t_DO
t_DV
t_TR
t_CSW
t_CSS
t_CSH
t_CH
t_CL
t_CP
CONDITIONS
C_DOUT = 50pF
C_DOUT = 50pF
C_DOUT = 50pF
MIN TYP MAX UNITS
1.1
µs
50
ns
80
ns
80
ns
50
ns
100
ns
0
ns
65
ns
65
ns
208
ns
4 _______________________________________________________________________________________