MAX11044 Datasheet, PDF (4/19 Pages) Maxim Integrated Products – 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs

4-/6-/8-Channel, 16-Bit,
Simultaneous-Sampling ADCs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = +4.75V to +5.25V, DVDD = +2.70V to +5.25V, V_AGNDS = V_AGND = V_DGND = 0V, V_REFIO = internal reference, C_RDC = 4 x
33µF, C_REFIO = 0.1µF, C_AVDD = 4 x 0.1µF || 10µF, C_DVDD = 3 x 0.1µF || 10µF; all digital inputs at DVDD or DGND, unless otherwise
noted, f_SAMPLE = 250ksps. T_A = -40°C to +85°C, unless otherwise noted. Typical values are at T_A = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
MAX11046, DVDD = 3.3V (Note 9)
7.3
mA
Digital Supply Current
I_DVDD MAX11045, DVDD = 3.3V (Note 9)
6.3
mA
MAX11044, DVDD = 3.3V (Note 9)
5.5
mA
Shutdown Current
I_DVDD
I_AVDD
10
µA
12
Power-Supply Rejection Ratio
PSRR VAVDD = 4.9V to 5.1V (Note 10)
±3
LSB
TIMING CHARACTERISTICS (Note 9)
CONVST Rise to EOC
Acquisition Time
CS Rise to CONVST Rise
CONVST Rise to EOC Rise
EOC Fall to CONVST Fall
t_CON Conversion time (Note 11)
t_ACQ
1
t_Q
Sample quiet time (Note 11)
500
t₀
t₁
CONVST mode B0 = 0 only (Note 12)
0
3
µs
1000
µs
ns
47
140
ns
ns
CONVST Low Time
t₂
CONVST mode B0 = 1 only
20
ns
CS Fall to WR Fall
t₃
0
ns
WR Low Time
t₄
20
ns
CS Rise to WR Rise
t₅
0
ns
Input Data Setup Time
t₆
10
ns
Input Data Hold Time
t₇
1
ns
CS Fall to RD Fall
t₈
0
ns
RD Low Time
t₉
30
ns
RD Rise to CS Rise
t₁₀
0
ns
RD High Time
t₁₁
10
ns
RD Fall to Data Valid
t₁₂
35
ns
RD Rise to Data Hold Time
t₁₃
(Note 12)
5
ns
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
See the Definitions section at the end of the data sheet.
INL is guaranteed at AVDD = 5.25V, for +25°C < T_A < +85°C. See the Input Range and Protection section and Typical
Operating Characteristics.
T_A = -40°C.
DNL at code > 8192 or < 57343 (offset binary encoded), or code > -24576 or < +24575 (two’s complement), is guaranteed
at AVDD = 5.25V, for +25°C < T_A < +85°C. See the Input Range and Protection section and Typical Operating
Characteristics.
DNL at code ≤ 8192 or ≥ 57343 (offset binary encoded), or code ≤ -24576 or ≥ +24575 (2’s complements), is guaranteed
at AVDD = 5.25V, for +25°C < T_A < +85°C. See the Input Range and Protection section and Typical Operating
Characteristics.
AC dynamics are guaranteed at AVDD = 5.25V, for +25°C < T_A < +85°C. See the Input Range and Protection section and
Typical Operating Characteristics.
Tested with alternating channels modulated at full scale and ground.
Note 8: See the Input Range and Protection section for more details.
Note 9: C_LOAD = 30pF on DB0–DB15 and EOC. Inputs (CH0–CH7) alternate between full scale and zero scale. f_CONV = 250ksps.
All data is read out.
Note 10: Defined as the change in positive full scale caused by a ±2% variation in the nominal supply voltage.
Note 11: It is recommended that RD, WR, and CS are kept high for the quiet time (t_Q) and conversion time (t_CON).
Note 12: Guaranteed by design.
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