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DS1642 Datasheet, PDF (4/13 Pages) Dallas Semiconductor – Nonvolatile Timekeeping RAM | |||
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DS1642
SETTING THE CLOCK
The 8th bit of the control register is the write bit. Setting the write bit to a 1, like the read bit, halts
updates to the DS1642 registers. The user can then load them with the correct day, date and time data in
24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock counters
and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The OSC bit is the MSB for the seconds registers. Setting it to
a 1 stops the oscillator.
FREQUENCY TEST BIT
Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the
oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the seconds register is
being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for access remain valid
(i.e., CE low, and OE low) and address for seconds register remain valid and stable.
CLOCK ACCURACY
The DS1642 is guaranteed to keep time accuracy to within ï±1 minute per month at 25ï°C. Dallas
Semiconductor calibrates the clock at the factory by using special calibration nonvolatile-tuning elements.
The DS1642 does not require additional calibration and temperature deviations will have a negligible
effect in most applications. For this reason, methods of field clock calibration are not available and not
necessary.
Table 2. REGISTER MAPâBANK1
ADDRESS B7
B6
B5
DATA
B4 B3
B2
B1
B0
FUNCTION
7FF
ââââââââ
Year
00â99
7FE
X X X â â â â â Month
01â12
7FD
X X ââââââ
Date
01â31
7FC
X FT X X X â â â
Day
00â23
7FB
X X ââââââ
Hour
00â59
7FA
X â â â â â â â Minutes
00â59
7F9
OSC â â â â â â â Seconds
00â59
7F8
W R X X X X X X Control
A
OSC = STOP BIT
W = WRITE BIT
R = READ BIT
X = UNUSED
FT = FREQUENCY TEST
Note: All indicated âXâ bits are not used but must be set to â0â during write cycle to ensure proper clock
operation.
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