DS1642 Datasheet, PDF (3/13 Pages) Dallas Semiconductor – Nonvolatile Timekeeping RAM

DS1642
CLOCK OPERATIONS–READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1642 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, the 7th most significant bit in the control register.
As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the
count, that is day, date, and time that was current at the moment the halt command was issued. However,
the internal clock registers of the double-buffered system continue to update so that the clock accuracy is
not affected by the access of data. All of the DS1642 registers are updated simultaneously after the clock
status is reset. Updating occurs within a second after the read bit is written to 0.
Figure 1. DS1642 BLOCK DIAGRAM
Table 1. TRUTH TABLE
V_CC
5V ±10%
<4.5V > V_BAT
<V_BAT
CE OE WE
V_IH X
X
V_IL
X
V_IL
V_IL V_IL V_IH
V_IL V_IH V_IH
XX X
XX X
MODE
Deselect
Write
Read
Read
Deselect
Deselect
DQ
High-Z
Data In
Data Out
High-Z
High-Z
High-Z
POWER
Standby
Active
Active
Active
CMOS Standby
Data Retention Mode
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