DS8007_11 Datasheet, PDF(37/41 Page) Maxim Integrated Products – Multiprotocol Dual Smart Card Interface 8kV (min) ESD Protection on Card Interfaces

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

DS8007_11 Datasheet, PDF (37/41 Pages) Maxim Integrated Products – Multiprotocol Dual Smart Card Interface 8kV (min) ESD Protection on Card Interfaces

◁

Multiprotocol Dual Smart Card Interface

Last Character to Transmit

The ISO UART implements a special control input that

allows an automatic switch from transmit mode

(UCR1.T/R = 1) to receive mode (UCR1.T/R = 0) upon

successful character transmission. The last character

to transmit (UCR1.LCT) bit must be set to 1 by host

software prior to writing the last character for transmis-

sion to UTR. Upon successful transmission of the char-

acter, the UCR1.T/R bit and the LCT bit are cleared by

hardware. When the LCT bit is used, the TBE/RBF bit is

not set at the end of the transmission.

Receive Mode

The ISO UART receive mode is in effect if the associat-

ed UCR1.T/R bit is 0. When the ISO UART is changed

to receive mode, the MSR.FE bit is set to 1 to indicate

that the receive FIFO is empty. When at least one

unread receive character exists in the FIFO, the FE bit

is cleared. When the FIFO, with depth defined by

FL2âFL0, is full, the TBE/RBF bit is set to 1 to indicate

that the receive buffer is full. Once a character is read

from a full FIFO, the RBF/TBE bit is cleared to indicate

that the FIFO is no longer full. The controller ready

(CRED) bit should be polled to assess data readiness

when reading from register URR at high frequencies.

Parity Check

The T = 1 protocol selection checks receive parity. For

T = 1, the parity error count bits (PEC2âPEC0) have no

function and the USR.PE bit are set on the first parity

error.

The T = 0 protocol selection also checks receive parity,

but allows setting of the USR.PE parity error bit to be

based upon detection of 1â8 parity errors. The

PEC2âPEC0 bits define the number of consecutive par-

ity errors that should be detected before setting

USR.PE.

The ISO UART implements a special control input that

allows testing for inverse parity. If the UCR1.FIP bit is

configured to 0 during receive mode, the ISO UART

tests for correct parity on each received character. If

UCR1.FIP is configured to 1, inverse parity is expected.

This control can be useful in testing that the ICC prop-

erly detects error signals generated by the DS8007 and

retransmits requested characters.

LAST CHARACTER TO TRANSMIT

LCT BIT WRITTEN TO 1 BY

SOFTWARE, THEN LOAD UTR.

TBE REMAINS 0, LCT AND

T/R BITS ARE BOTH CLEARED

TO 0 BY HARDWARE.

I/O

LAST CHARACTER

TBE/RBF BIT

LCT BIT

T/R BIT

Figure 15. Last Character to Transmit

______________________________________________________________________________________ 37

▷