DS8007_11 Datasheet, PDF(32/41 Page) Maxim Integrated Products – Multiprotocol Dual Smart Card Interface 8kV (min) ESD Protection on Card Interfaces

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DS8007_11 Datasheet, PDF (32/41 Pages) Maxim Integrated Products – Multiprotocol Dual Smart Card Interface 8kV (min) ESD Protection on Card Interfaces

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Multiprotocol Dual Smart Card Interface

ISO UART Implementation

Reset Operation

The CSR.RIU control bit resets the ISO UART. The

CSR.RIU must be reset prior to any activation. CSR.RIU

must be returned to 1 by software before any UART

action can take place.

Synchronous Mode

The synchronous mode of operation is invoked by set-

ting the synchronous/asynchronous card select bit (for

a given card interface) to logic 1. In the synchronous

mode of operation, the associated I/Ox card interface

data is transferred by the LSb of the UART

transmit/receive registers (UTR and URR). In this mode,

the host device using the CCRx.SC register bit manual-

ly controls the CLKx pin for the selected card interface.

Switching to the synchronous mode or vice versa is

allowed at any time when the card is active. However, it

is the responsibility of the host software/firmware to

ensure that the current transmission is concluded

before switching. If software configures an active card

for synchronous mode, and then activates another

card, the I/O pin on the previously active card goes to a

high-impedance state with a weak pullup (high). The

newly selected interface (if configured to synchronous

mode) takes on UTR.0.

The AUX card interface does not have an associated

CLK signal, so the CCRAUX.SC bit does not control an

output signal when the synchronous mode of operation

is in effect. The handshake between the host and the

auxiliary smart card interface is accomplished through

the auxiliary interrupt input (INTAUX) and the INT pins.

The MSR.INTAUX bit reflects the state of the INTAUX pin.

If the UCR2.DISAUX bit is cleared to 0, a change on the

INTAUX input pin results in the assertion of INT output

pin. The host software/firmware establishes the commu-

nication protocol and controls when to transmit/receive

data in response to the interrupt. If the UCR2.DISAUX bit

is set to 1, the INT pin is not asserted, and the host soft-

ware/firmware must examine the INTAUX bit in the MSR

Asynchronous Mode

The asynchronous mode of operation is the reset

default mode for all card interfaces and is selected

when the synchronous/asynchronous card select bit

(for a given card interface) is configured to logic 0. The

I/Ox card interface signal is used for asynchronous

half-duplex data communication between the host-con-

trolled ISO UART and the external smart card. The host

device can optionally stop the CLKx signal in the high

or low state while the card is active using the

CCRx.CST and CCRx.SHL register bits.

ETU Generation and Timing

The basic unit of time for asynchronous mode commu-

nication on the I/Ox signal is the elementary time unit

(ETU). The ETU is defined within the ISO UART as a

function of the fCLK frequency that is configured for the

card interface (i.e., the same fCLK that can be sourced

to the CLKx pin of an associated card interface A or B).

In addition to receiving fCLK from the clock generation

block, the ISO UART additionally receives a 2 x fCLK

frequency if CCRx.AC2âAC0 â 000b. The host device

can select whether fCLK or 2 x fCLK is used for ETU

generation by using the clock UART (CKU) select bit.

When CKU = 0, fCLK is used, while 2 x fCLK is used

when CKU = 1. One exception exists when

CCRx.AC2âAC0 = 000b, in which case, only fCLK is

sourced to the UART and the CKU bit setting has no

effect on the duration of an ETU.

The basic clock that is selected for ETU generation by

the CKU bit is further prescaled by a factor or 31 or 32.

The prescaler select control (PSC) bit makes this

prescaler selection. When PSC is configured to logic 0,

the prescale setting is 31. When PSC is configured to

logic 1, the prescale setting is 32. The output of the

clock prescaler drives an 8-bit autoreload down

counter. The autoreload value for the downcounter is

configured by the host device through the

Programmable Divider Register (PDR). The interval pro-

vided by this downcounter defines the ETU duration for

the selected card. Figure 11 shows a diagram of ETU

generation. All the asynchronous character

transmit/receive operations are defined in terms of ETU

(e.g., 10.5 ETU, 10.25 ETU, etc).

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