DS26556_07 Datasheet, PDF (362/368 Pages) Maxim Integrated Products – 4-Port Cell/Packet Over T1/E1/J1 Transceiver

DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
19.4 System Interface AC Characteristics
The generic timing definitions shown in Figure 19-1, Figure 19-2, Figure 19-3, and Figure 19-6 apply to this
interface.
Table 19-4 System Interface Level 2 Timing
(V_DD = 3.3V ±5%, T_j = -40°C to +125°C.)
SIGNAL NAME(S)
SYMBOL
DESCRIPTION
RSCLK and TSCLK
f1
Clock frequency (1/t1) (Note 1)
RSCLK and TSCLK
t2/t1
Clock duty cycle (Note 1)
RSCLK and TSCLK
t3
Rise/fall times (Notes 1, 2)
RADR and REN
t5
Hold time from RSCLK (Note 1)
RADR and REN
t6
Setup time to RSCLK (Note 1)
RDATA, RPRTY, RPXA,
RSOX, REOP, RVAL,
t7
Delay from RSCLK (Notes 1, 3)
RMOD, and RERR
RDATA, RPRTY, RPXA,
RSOX, REOP, RVAL,
RMOD, and RERR
t8
From high-Z delay from RSCLK
(Notes 1, 3)
RDATA, RPRTY, RPXA,
RSOX, REOP, RVAL,
RMOD, and RERR
t9
To high-Z delay from RSCLK
(Notes 1, 3)
TDATA, TPRTY, TADR,
TEN, TSOX, TEOP,
t5
Hold time from TSCLK (Note 1)
TMOD, and TERR
TDATA, TPRTY, TADR,
TEN, TSOX, TEOP,
t6
Setup time to TSCLK (Note 1)
TMOD, and TERR
TPXA and TSPA
t7
Delay from TSCLK (Notes 1, 3)
TPXA and TSPA
t8
From high-Z delay from TSCLK
(Notes 1, 3)
TPXA and TSPA
t9
To high-Z delay from TSCLK
(Notes 1, 3)
MIN TYP MAX UNITS
0
52
MHz
40 50 60
%
2
ns
0
ns
3.5
ns
2
12
ns
2
12
ns
2
15
ns
0
ns
3.5
ns
2
12
ns
2
12
ns
2
15
ns
Note 1:
Note 2:
Note 3:
The input/output timing reference level for all signals is V_DD/2.
Rise and fall times are measured at output side with the output unloaded. Rise time is measured from 20% to 80% V_OH. Fall time
is measured from 80% to 20% V_OH.
These times are met with a 30pF, 300Ω load on the associated output pin.
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