DS26556_07 Datasheet, PDF (113/368 Pages) Maxim Integrated Products – 4-Port Cell/Packet Over T1/E1/J1 Transceiver

DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.2 Cell / Packet Register Descriptions
The register descriptions are divided into separate register block sections. Bits that are underlined are read-only;
all other bits are read-write. Configuration registers and bits can be written to and read from during a data path
reset (LDRST bit = 0), however, all changes to these bits will be ignored during the data path reset. As a result, all
bits requiring a 0 to 1 transition to initiate an action must have the transition occur after the data path reset has
been removed.
All counters stop counting at their maximum count. A counter register is updated by asserting (low to high
transition) the associated performance monitoring update signal (xxPMU). During the counter register update
process, the associated performance monitoring status signal (xxPMS) will be deasserted. The counter register
update process consists of loading the counter register with the current count, resetting the counter, forcing the
zero count status indication low for one clock cycle, and then asserting xxPMS. No events shall be missed during
an update procedure.
A latched bit is set when the associated event occurs, and remains set until it is cleared. Once cleared, a latched
bit will not be set again until the associated event reoccurs (goes away and comes back). A latched on change bit
is a latched bit that is set when the event occurs, and when it goes away. A latched status bit is cleared when the
register is selected (register addressed and associated BSxx high), the appropriate byte enable (LBE or UBE) is
high, a logic one is present on the corresponding DI[x], and the LSRCK signal goes high.
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