DS80C410_09 Datasheet, PDF (36/102 Pages) Maxim Integrated Products – Network Microcontrollers with Ethernet and CAN

DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
4 clocks per cycle to 1024 clocks per cycle. For example, 40MHz standard operation has a machine cycle rate of
10MHz. In PMM, at the same external clock speed, software can select a 39kHz machine cycle rate, considerably
reducing power consumption. The microcontroller can be configured to automatically switch back from PMM to the
faster mode in response to external interrupts or serial port activity. The DS80C410 provides the ability to place the
CPU into an idle state or an ultra-low-power stop-mode state. As protection against brownout and power-fail
conditions, the microcontroller is capable of issuing an early warning power-fail interrupt and can generate a power-
fail reset.
When the internal ROM is disabled, the DS80C410 defaults to true 8051-memory compatibility on power up.
However, the microcontroller is most powerful when taking advantage of its enhanced memory architecture. The
DS80C410 has a selectable 10-bit stack pointer that can address up to 1kB of on-chip SRAM stack space for
increased code efficiency. It can be operated in a 24-bit paged or 24-bit contiguous address mode, giving access to
a much larger address range than the standard 16-bit address mode. Support for merged program and data
memory access allows in-system programming, and it can be configured to internally demultiplex data and the
lowest address byte, thereby eliminating the need for an external latch and potentially allowing the use of slower
memory devices.
80C32 COMPATIBILITY
The DS80C410 is a CMOS 80C32-compatible microcontroller designed for high performance. Every effort has
been made to keep the core device familiar to 80C32 users while adding many enhanced features. The DS80C410
provides the same timer/counter resources, full duplex serial port, 256 Bytes of scratchpad RAM, and I/O ports as
the standard 80C32. Timers default to 12 oscillator clocks per tick operation to keep timing compatible with original
8051 systems. New hardware functions are accessed using special function registers (SFRs) that do not overlap
with standard 80C32 locations. All instructions perform exactly the same functions as their 8051 counterparts. Their
effect on bits, flags, and other status functions is identical. Because the device runs the standard 8051 instruction
set, in general, software written for existing 80C32-based systems work on the DS80C410. The primary exceptions
are related to timing-critical issues, since the high-performance core of the microcontroller executes instructions
much faster than the original, both in absolute and relative number of clocks.
The relative time of two DS80C410 instructions might differ from the traditional 8051. For example, in the original
architecture the “MOVX A, @DPTR” instruction and the “MOV direct, direct” instruction required the same amount
of time: two machine cycles or 24 oscillator cycles. In its default configuration (machine cycle = 4 oscillator cycles),
the DS80C410 executes the “MOVX A, @DPTR” instruction in as little as two machine cycles or 8 oscillator cycles,
but the “MOV direct, direct” uses three machine cycles or 12 oscillator cycles. While both are faster than their
original counterparts, they now have different execution times. Examine the timing of each instruction for familiarity
with the changes. Note that a machine cycle now requires just 4 clocks, and provides one ALE pulse per cycle.
Most instructions require only one or two cycles, but some require as many as four or five. Refer to the High-Speed
Microcontroller User’s Guide and the High-Speed Microcontroller User’s Guide: Network Microcontroller
Supplement for individual instruction-timing details and for calculating the absolute timing of software loops. Also
remember that the counter/timers default to run at the traditional 12 clocks per increment. This means that timer-
based events still occur at the standard intervals, but that code now executes at a higher speed relative to the
timers. Timers optionally can be configured to run at the faster 4 clocks per increment to take advantage of faster
controller operation.
Memory interfacing can be performed identically to the standard 80C32. The high-speed nature of the DS80C410
core slightly changes the interface timing, and designers are advised to consult the timing diagrams in this data
sheet for more information.
This data sheet provides only a summary and overview of the DS80C410. Detailed descriptions are available in the
corresponding user’s guide. This data sheet assumes a familiarity with the architecture of the standard 80C32. In
addition to the basic features of that device, the DS80C410 incorporates many new features.
PERFORMANCE OVERVIEW
The DS80C410’s higher performance comes not just from increasing the clock frequency but also from a more
efficient design. This updated core removes the dummy memory cycles that are present in a standard, 12 clock-
per-machine cycle 8051. In the DS80C410, a machine cycle requires only 4 clocks. Thus the fastest instruction, 1
machine cycle in duration, executes three times faster for the same crystal frequency. The majority of instructions
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