MAX13301 Datasheet, PDF (34/37 Pages) Maxim Integrated Products – 4-Channel, Automotive Class D Audio Amplifier Feedback After the Filter

4-Channel, Automotive Class D Audio Amplifier
Charge-Pump Capacitor Selection
Use capacitors with an ESR less than 100mI for opti-
mum performance. Low-ESR ceramic capacitors mini-
mize the output resistance of the charge pump. For best
performance over the extended temperature range,
select capacitors with an X7R dielectric. The typical
value is 1FF.
Flying Capacitor (CFLY)
The value of the flying capacitor (CFLY) affects the load
regulation and output resistance of the charge pump. A
CFLY value that is too small degrades the device’s ability
to provide sufficient current drive. Increasing the value of
CFLY improves load regulation and reduces the charge-
pump output resistance to an extent. Use a 50V, 1FF
ceramic capacitor for CFLY.
Supply Bypassing, Layout, and Grounding
Proper layout and grounding are essential for optimum
performance. Use large traces for the power-supply
inputs and amplifier outputs to minimize losses due
to parasitic trace resistance. Large traces also aid in
moving heat away from the package. Proper ground-
ing improves audio performance, minimizes crosstalk
between channels, and prevents any switching noise
from coupling into the audio signal. Connect PGND and
GND together at a single point on the PCB. Route all
traces that carry switching transients away from GND
and the traces/components in the audio signal path.
Bypass VDD to GND with a 10FF ceramic capacitor
and VDD5 to PGND with a 0.1FF ceramic capacitor.
Each PVDD is paired with two PGNDs for local supply
bypassing. Bypass each PVDD-PGND pair with 0.1FF
and 4.7FF ceramic capacitors. Table 35 shows the four
PVDD-PGND pairs.
Place an additional 1000FF low-ESR electrolytic capaci-
tor from pins 1 and 48 to PGND and from pins 24 and
25 to PGND.
Use large, low-resistance output traces. Current drawn
from the outputs increases as load impedance decreas-
es. High output trace resistance decreases the power
delivered to the load. Large output, supply, and PGND
traces allow more heat to move from the device to the air,
decreasing the thermal impedance of the circuit.
Table 33. PVDD and PGND Pairs
PVDD PIN NUMBER
1
48
24
25
PGND PIN NUMBER
9 and 10
39 and 40
11 and 12
37 and 38
The feedback connections are sensitive to inductor mag-
netic field interference, so route these traces away from
the inductors and noisy traces connected to OUT_ and
the charge pump.
Refer to the MAX13301 Evaluation Kit for a PCB layout
example.
Thermal Information
The device requires external heatsinking for applica-
tions that dissipate more than 1333.3mW. The top side
exposed pad is the primary heat conduction path on the
device. The thermal resistance of the heatsink is calcu-
lated from the following equation:
θ_HS
≤



T_J - T_A
P_DISS



−
θ _JC
−
θ _CH
where:
TJ = +150°C
TA = Ambient Operating Temperature
BJC = 1°C/W
BCH = Thermal resistance of the thermal interface used
between the top side exposed pad and the heatsink
PDISS = Estimated power dissipation of the device
The estimated power dissipation can be calculated from
the following equation based on the desired continuous
output power, POUT, of the application, the typical effi-
ciency, E, and the number of output channels used, N.
P_DISS
≤
1


η
−
1^

× N × P_OUT
34