DS3161 Datasheet, PDF (323/384 Pages) Maxim Integrated Products – Single/Dual/Triple/Quad ATM/Packet PHYs for DS3/E3/STS-1

DS3161/DS3162/DS3163/DS3164
Register Name:
Register Description:
Register Address:
Bit #
15
Name
--
Default
0
Bit #
7
Name
--
Default
0
FF.RLCR
FIFO Receive Level Control Register
(1,3,5,7)92h
14
13
12
11
--
RFAE5 RFAE4 RFAE3
0
0
1
0
6
5
4
3
--
RFAF5
RFAF4
RFAF3
0
0
1
0
10
RFAE2
0
2
RFAF2
0
9
RFAE1
0
1
RFAF1
0
8
RFAE0
0
0
RFAF0
0
Bits 13 to 8: Receive FIFO Almost Empty Level (RFAE[5:0]) – In POS-PHY packet processing mode, these six
bits indicate the maximum number of four byte groups that can be stored in the Receive FIFO for it to be
considered "almost empty". E.g., a value of 30 (1Eh) results in the FIFO being "almost empty" when it contains 120
(78h) bytes or less. In cell processing mode, RFAE[5:2] are ignored, and RFAE[1:0] indicate the maximum number
of cells that can be stored in the Receive FIFO for it to be considered "almost empty".
Bits 5 to 0: Receive FIFO Almost Full Level (RFAF[5:0]) – In POS-PHY packet processing mode, these six bits
indicate the maximum number of four byte groups that can be available in the Receive FIFO for it to be considered
"almost full". E.g., a value of 30 (1Eh) results in the FIFO being "almost full" when it has 120 (78h) bytes or less
available. In cell processing mode, these bits are ignored.
Register Name:
Register Description:
Register Address:
Bit #
15
Name
--
Default
0
Bit #
7
Name
--
Default
0
FF.RFPAC
FIFO Receive Port Address Control Register
(1,3,5,7)94h
14
13
12
11
10
--
--
--
--
--
0
0
0
0
0
6
5
4
3
2
--
--
RPA4
RPA3
RPA2
0
0
0
0
0
9
--
0
1
RPA1
0
8
--
0
0
RPA0
0
Bits 4 to 0: Receive FIFO System Port Address (RPA[4:0]) – These five bits set the Receive FIFO system
interface port address used to poll the Receive FIFO for fill status, and select it for data transfer. Each port in the
device must have a different port address. In Level 2 mode, if bits RPA[4:0] are set to a value of 1Fh, the port is
disabled.
Register Name:
Register Description:
Register Address:
Bit #
15
Name
--
Bit #
7
Name
--
FF.RSRL
FIFO Receive Status Register Latched
(1,3,5,7)98h
14
13
12
11
10
--
--
--
--
--
6
5
4
3
2
--
--
--
--
--
9
8
--
--
1
0
--
RFOL
Bit 0: Receive FIFO Overflow Latched (RFOL) – This bit is cleared when a logic one is written to this bit, and set
when a Receive FIFO overflow condition occurs. An overflow condition results in a loss of data.