DS3161 Datasheet, PDF (125/384 Pages) Maxim Integrated Products – Single/Dual/Triple/Quad ATM/Packet PHYs for DS3/E3/STS-1

DS3161/DS3162/DS3163/DS3164
Figure 10-13. DS3 M23 (with C-bits used as payload) Frame
84
X_{1 bits} F₁₁
169
bits
F₁₂
X₂
F₂₁
F₂₂
P₁
F₃₁
F₃₂
P₂
F₄₁
F₄₂
M₁
F₅₁
F₅₂
M₂
F₆₁
F₆₂
M₃
F₇₁
F₇₂
169
bits
F₁₃
169
bits
F₂₃
F₃₃
F₄₃
F₅₃
F₆₃
F₇₃
F₁₄
84
bits
F₂₄
F₃₄
F₄₄
F₅₄
F₆₄
F₇₄
7 Sub-
Frames
680 Bits
10.5.11.3 E3 G.751 Direct and PLCP Mapping
For direct mapping into E3 G.751 frames, ATM cells and HDLC packets are bit aligned. ATM cells can also be
PLCP mapped to the E3 G.751 frame. When E3 PLCP mapping is used, the first four bits of the payload (E3 frame
bits 13,14,15 and 16) are forced to be 1100 and the rest of the payload is used for the PLCP frame which is
transmitted byte aligned and the NAD bit is ignored.
Figure 10-14. E3 G.751 Frame
FAS A N
376 Payload Bits
384 Payload Bits
384 Payload Bits
384 Payload Bits
4 Rows
384 bits
In E3 PLCP framing, the ATM cell is always cell aligned into the PLCP frame, HDLC packets can not be mapped
into PLCP frames. The E3 PLCP frame can only be mapped into a E3 G.751 frame. The NAD control bit is ignored.